Diffusion Break Gap Fill for Seam-Free High-Aspect-Ratio Features
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Solution Overview
Problem
Conventional methods struggle to deposit seam-free and void-free films in high aspect ratio features of semiconductor devices, particularly in FinFETs and GAA structures, leading to parasitic capacitance and off-state leakage issues.
Innovation Solution
A method involving etching a diffusion break in a gate region, flowing silicon-containing and hydrogen-containing precursors to form a modified silicon-containing layer, and reacting it with radicals from a remote plasma source to create a silicon nitride dielectric layer that fills the diffusion break, ensuring a seam-free and void-free fill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used in high aspect ratio features, then the manufacturing process is simple, but the film quality deteriorates with seams and voids
Solution Approach 1:
The deposition process is divided into multiple sequential stages: initial deposition to form a base layer, modification treatment with hydrogen-containing precursor, etching of sidewall regions, densification treatment, and final deposition to complete the fill. This segmentation allows each stage to optimize for its specific function, achieving seamless void-free films in high aspect ratio features while managing process complexity through systematic breakdown of the overall deposition task
Solution Approach 2:
Before the final film deposition, preliminary actions are performed including: forming a base silicon-containing layer, treating it with hydrogen-containing precursor to modify surface properties, selectively etching sidewall regions to prevent void formation, and densifying the layer structure. These preliminary actions prepare the substrate and initial film structure to receive subsequent material without forming defects, enabling high-quality fill in high aspect ratio features
2Productivity
If device sizes are reduced to increase circuit density, then the circuit density improves, but the film deposition quality deteriorates
Solution Approach 1:
The deposition and treatment process applies different conditions to different regions of the high aspect ratio feature. The modification treatment with hydrogen-containing precursor and the etching process create localized variations in film structure and composition, with the bottom and sidewall regions receiving different treatments than the top regions. This local quality control ensures proper film formation throughout the entire high aspect ratio feature despite reduced device dimensions
Solution Approach 2:
The process utilizes parameter changes including temperature variations during deposition and treatment, pressure adjustments in the deposition chamber, and controlled modification of film composition through hydrogen-containing precursor treatment. These parameter changes enable adaptation of the deposition process to maintain film quality in progressively smaller device features with higher aspect ratios
3Strength
If diffusion breaks are filled in high aspect ratio features, then the channel stress is enhanced, but parasitic capacitance and off-state leakage increase due to seams and voids
Solution Approach 1:
The process converts potential harmful effects into beneficial outcomes by using hydrogen-containing precursor treatment to modify the silicon-containing layer in a way that prevents void formation. The selective etching of sidewall regions, which could be seen as removing material, actually prevents future void formation by creating a tapered structure that facilitates complete fill. These actions transform potential defects into mechanisms that ensure seamless film formation, enhancing channel stress without introducing parasitic capacitance or off-state leakage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a seamless and void-free fill in diffusion breaks with aspect ratios greater than 10:1, enhancing channel stress and reducing parasitic capacitance and off-state leakage in semiconductor devices.
Implementation Method 1
reacting the modified silicon-containing layer with one or more radicals generated by a remote plasma source
Implementation Method 2
reacting the modified silicon-containing layer with one or more radicals generated by a remote plasma source to form a silicon nitride (SiN) dielectric layer
Implementation Method 3
forming plasma effluents of a silicon-containing precursor and flowing the plasma effluents of the silicon-containing precursor over the substrate to form a silicon-containing layer
Implementation Method 4
flowing a hydrogen-containing precursor over the silicon-containing layer to form a modified silicon-containing layer
Data Source
AI summary
Described are semiconductor devices, e.g., PMOS and/or NMOS, with improved stress in the channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel extending between the source region and the drain region, and a diffusion break patterned through the device. The self-aligned diffusion break opening is gap filled a stressed dielectric material using a densified seam-free silicon-containing material gap fill process.