Metal Contact Diffusion-Break Layout for Frontside-Backside Power Routing
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Solution Overview
Problem
Existing approaches for power connection between the frontside and backside of semiconductor chips, such as through buried power rails and TSVs, are limited in routing capability, especially for stacked transistors, and do not allow for power lines at the frontside at the BEOL level.
Innovation Solution
A semiconductor structure with metal connections between transistors on a substrate, where the source/drain regions are replaced by metal connections, and the metal connections are electrically isolated using nanosheets and spacers, allowing for connections between frontside and backside metal contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If buried power rails and TSVs are used for power connection between frontside and backside, then power connection is achieved, but routing capability is limited
Solution Approach 1:
The patent transitions from traditional planar power distribution to three-dimensional power connection by forming metal connections that extend from the frontside through the substrate to the backside. This vertical dimension enables power lines at the BEOL level on the frontside while maintaining routing flexibility, resolving the contradiction between routing capability and connection structure complexity.
Solution Approach 2:
The metal connection is nested within a multi-layer structure comprising nanosheets, spacers, and dielectric layers. The nanosheets are positioned between the metal connection and active transistor regions, with spacers providing additional isolation. This nested arrangement enables complex power routing while maintaining organizational structure and reducing overall system complexity.
2Adaptability or versatility
If metal connections replace source/drain regions, then routing capability is enhanced, but transistor structure becomes modified
Solution Approach 1:
The patent applies different structural configurations to different regions: dummy transistors have their source/drain regions replaced by metal connections for routing purposes, while active transistors maintain traditional source/drain structures. The nanosheets are selectively positioned to isolate metal connections only in dummy transistor regions, preserving manufacturing precision for active devices while enabling enhanced routing where needed.
3Reliability
If nanosheets and spacers are used for electrical isolation, then electrical isolation is achieved, but device structure complexity increases
Solution Approach 1:
The nanosheets act as intermediary elements positioned between the metal connections and the active transistor regions. These nanosheets provide electrical isolation while maintaining a relatively simple structural footprint. The spacers further mediate the isolation between adjacent nanosheets, creating a modular isolation structure that enhances reliability without excessive complexity increase.
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors. A method of forming the same is also provided.