Diffusion Cut Stressors for Stacked GAA Transistor Isolation

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Solution Overview

Problem

The challenge in forming stacked semiconductor devices is the localized stress caused by diffusion cut materials, which can negatively impact the operation of adjacent devices, especially in stacked transistors where the stress gradient affects n-channel and p-channel devices differently.

Innovation Solution

The use of compressive and tensile stressor materials in diffusion cut structures adjacent to stacked transistors to provide beneficial stress gradients and isolate semiconductor devices, improving the mobility of minority carriers and device operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If diffusion cut materials are used to isolate stacked semiconductor devices, then device isolation is improved, but localized stress is generated that negatively impacts device operation

Engineering Contradiction:
Improvedevice isolationVSAvoidlocalized stress
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies different stressor materials (compressive and tensile) to different regions adjacent to the stacked transistors. Specifically, compressive stressor material is applied to one side and tensile stressor material to the other side, creating localized stress gradients that counteract the harmful localized stress from diffusion cut materials while maintaining device isolation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent converts the harmful localized stress effect into a beneficial one by intentionally introducing stressor materials that create controlled stress gradients. These stress gradients improve carrier mobility in the semiconductor devices, transforming the originally harmful stress effect into a performance-enhancing mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If stressor materials are applied to improve carrier mobility, then device performance is enhanced, but device complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stressor materials serve multiple functions: they provide beneficial stress gradients to improve carrier mobility, act as diffusion barriers, and contribute to device isolation. This multi-functionality reduces the need for separate structures for each function, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses composite material structures where stressor materials are integrated with diffusion barrier materials and isolation structures. This composite approach allows multiple functions to be achieved within a unified structure, managing complexity while delivering enhanced device performance.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the operational performance of stacked semiconductor devices by applying appropriate stress to n-channel and p-channel devices, improving carrier mobility and device isolation, thereby addressing the stress-related challenges in stacked transistor configurations.

Implementation Method 1

The use of compressive and tensile stressor materials in diffusion cut structures adjacent to stacked transistors to provide beneficial stress gradients and isolate semiconductor devices, improving the mobility of minority carriers and device operation.

Methodology Applied
Scientific EffectStress gradient effect:

Data Source

PatentUS20230420562A1Diffusion cut stressors for stacked transistors
Publication Date: 2023.12.28 INTEL CORP
  • US20230420562A1 patent drawing
  • US20230420562A1 patent drawing
  • US20230420562A1 patent drawing

AI summary

Techniques are provided herein to form non-planar semiconductor devices in a stacked transistor configuration adjacent to stressor materials. In one example, an n-channel device and a p-channel device may both be gate-all-around transistors each having any number of nanoribbons extending in the same direction, where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and both ends of the p-channel device. On the opposite side of the stacked source or drain regions (e.g., opposite from the nanoribbons), stressor materials may be used to fill the gate trench in place of additional semiconductor devices. The stressor materials may include, for instance, a compressive stressor material adjacent to the p-channel device and/or a tensile stressor material adjacent to the n-channel device. The stressor material(s) may form or otherwise be part of a diffusion cut structure.