Diffusion Retardation Layer for Multi-Gate Transistor Leakage
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Solution Overview
Problem
Multi-gate transistors, such as FinFETs and MBC transistors, face challenges with dopant diffusion into channel regions, leading to leakage paths and reduced device performance due to the diffusion of dopants from source/drain features into the channel and anti-punch-through regions.
Innovation Solution
Incorporating an outer epitaxial layer doped with arsenide as a diffusion retardation layer, spaced apart from an inner epitaxial feature doped with phosphorus, to prevent dopant diffusion into the channel and anti-punch-through regions, thereby reducing leakage and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate structures are used to improve gate control and reduce off-state current, then device performance is improved, but dopant diffusion into channel regions creates leakage paths
Solution Approach 1:
An outer epitaxial layer doped with arsenide is introduced as an intermediary barrier between the phosphorus-doped inner epitaxial layer and the channel region. This intermediate layer prevents phosphorus diffusion into the channel while maintaining the multi-gate structure's gate control benefits, thereby eliminating leakage paths without sacrificing device performance.
Solution Approach 2:
The source/drain structure employs a composite epitaxial layer system with two distinct doped layers: an inner layer doped with phosphorus and an outer layer doped with arsenide. This composite structure combines the benefits of both dopants while using the arsenide layer's lower diffusivity to prevent harmful phosphorus migration into the channel region.
2Reliability
If dopant concentration in source/drain features is increased to improve device performance, then electrical characteristics are enhanced, but dopant diffusion into channel and anti-punch-through regions increases
Solution Approach 1:
The arsenide-doped outer epitaxial layer serves as a diffusion barrier that mediates between the high-concentration phosphorus-doped inner layer and the channel region. This intermediary structure allows high dopant concentration in the source/drain region to improve electrical characteristics while preventing uncontrolled diffusion into sensitive channel and anti-punch-through regions.
Solution Approach 2:
Different dopant concentrations and types are applied locally within the source/drain structure: high phosphorus concentration in the inner epitaxial layer for electrical performance, and lower arsenide concentration in the outer layer for diffusion control. This local differentiation of dopant properties enables simultaneous optimization of electrical characteristics and dopant distribution precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of an arsenide-doped outer epitaxial layer effectively blocks phosphorus diffusion from the inner epitaxial feature, reducing n-type dopant concentration in the channel and anti-punch-through regions, resulting in smaller leakage and enhanced device performance.
Implementation Method 1
Incorporating an outer epitaxial layer doped with arsenide as a diffusion retardation layer, spaced apart from an inner epitaxial feature doped with phosphorus, to prevent dopant diffusion into the channel and anti-punch-through regions
Data Source
AI summary
A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.