Diffusion Topography Engineering for CMOS Profile Control
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Solution Overview
Problem
Conventional MOS device fabrication methods face challenges in profile control at the boundary of shallow trench isolation and diffusion regions, leading to issues like reverse narrow channel effects, corner gate leakage, and unfavorable stress, which degrade device performance, especially at smaller device widths.
Innovation Solution
The implementation of diffusion topography engineering (DTE) involves forming semiconductor structures with rounded, T-shaped, or slanted diffusion regions using hydrogen-containing ambients and stressed dielectric layers to optimize stress in the channel regions, improving the balance between source/drain resistance and junction depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If conventional STI formation processes are used, then trench isolation structures are formed, but undesirable divots are created at the boundary of STI regions and diffusion regions leading to reverse narrow channel effects and corner gate leakage
Solution Approach 1:
The patent applies curvature by forming rounded corners at the boundaries of diffusion regions and STI regions, replacing sharp corners with curved surfaces. This is achieved through selective oxidation processes that preferentially oxidize silicon at corners and edges, followed by removal of oxidized material, creating a smooth rounded profile that eliminates the divots and sharp corners causing RNCE and gate leakage
Solution Approach 2:
The patent changes physical parameters such as oxidation time, temperature, and atmospheric composition to control the rounding process. By adjusting these parameters, the degree of corner rounding can be precisely controlled to achieve optimal profiles that eliminate harmful effects while maintaining device geometry requirements
2Stress or pressure
If oxidation processes are performed along sidewalls of STI regions during post-gapfill thermal cycle, then stress relief is achieved, but unfavorable compressive STI stress is induced that significantly degrades device performance at small device widths
Solution Approach 1:
The patent applies local quality by selectively applying stress relief measures only at specific locations where needed. Rounded corners are formed specifically at the STI-diffusion boundaries where stress concentration occurs, while the bulk STI regions maintain their structural integrity. This localized approach provides stress relief at critical points without inducing unwanted compressive stress throughout the entire STI structure
3Stress or pressure
If recesses are introduced into source/drain regions for engineering diffusion region profiles, then favorable stress can be induced in channel regions improving MOS device performance, but the balance between source/drain resistance and junction depth is degraded and source/drain-to-substrate leakage is induced due to silicide punch-through
Solution Approach 1:
The patent applies curvature by forming rounded corners at the boundaries of diffusion regions and STI regions, replacing sharp corners with curved surfaces. This is achieved through selective oxidation processes that preferentially oxidize silicon at corners and edges, followed by removal of oxidized material, creating a smooth rounded profile that eliminates the divots and sharp corners causing RNCE and gate leakage
Solution Approach 2:
The patent changes physical parameters such as oxidation time, temperature, and atmospheric composition to control the rounding process. By adjusting these parameters, the degree of corner rounding can be precisely controlled to achieve optimal profiles that eliminate harmful effects while maintaining device geometry requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
DTE enhances device performance by reducing leakage currents and improving drive currents by 24-27% and delay time by 10% compared to conventional methods, while minimizing silicide punch-through and enhancing gate dielectric integrity.
Implementation Method 1
the first and the second stressed dielectric layers have substantially different stresses. Preferably, the first MOS device is an NMOS device, and the second MOS device is a PMOS device, wherein the first dielectric layer has an inherent tensile stress, and the second dielectric layer has an inherent compressive stress
Data Source
AI summary
Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.