Digit Line Contact Geometry for Memory Density
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Solution Overview
Problem
As semiconductor devices shrink, the increasing proximity of digit line contacts leads to elevated coupling capacitances, reducing the reliability of memory cells due to unwanted current and voltage distribution between neighboring memory cells, which complicates the scaling of memory devices.
Innovation Solution
The formation of semiconductor devices with substantially unetched word line caps having vertical and horizontal surfaces, which reduces the surface area of digit line contacts, thereby decreasing coupling capacitance between adjacent contacts, is achieved through a selective etching process that preserves the word line caps, maintaining their horizontal and vertical surfaces and transition edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digit line contacts are positioned closer together to increase memory density, then feature density increases, but coupling capacitance between adjacent contacts increases reducing reliability
Solution Approach 1:
The patent applies local quality by creating an asymmetric opening geometry where the floor is non-planar with a first region at a different elevation than a second region. This local variation in the opening structure allows different portions of the digit line contact to have different electrical characteristics, specifically reducing coupling capacitance in critical areas while maintaining overall high density through close contact spacing.
Solution Approach 2:
The patent introduces a vertical dimension to the contact opening structure by creating a non-planar floor with multiple elevation regions. This vertical stratification allows the digit line contacts to be positioned closer horizontally while the elevated portions provide electrical isolation, effectively using the third dimension to resolve the coupling capacitance issue that would normally prevent such close spacing.
2Ease of manufacture
If conventional etching processes are used to form digit line contact openings, then manufacturing simplicity is maintained, but coupling capacitance between adjacent contacts increases
Solution Approach 1:
The patent applies preliminary action by forming the non-planar floor structure with elevated regions before completing the digit line contact formation. This pre-established geometric feature is created through selective etching that preserves certain areas at higher elevations, which then serves to reduce coupling capacitance during subsequent contact formation without requiring additional complex processing steps.
Solution Approach 2:
The patent changes the geometric parameters of the contact opening by creating a non-planar floor with specific elevation differences between regions. This parameter modification—specifically the vertical displacement creating elevated portions—directly reduces the coupling capacitance between adjacent digit line contacts while maintaining manufacturing feasibility through adapted etching processes.
Data Source
AI summary
A semiconductor device comprises laterally-neighboring word lines having respective word line caps thereon, an active region between the laterally-neighboring word lines and word line caps, an insulating material and a semiconductive material adjacent the word line caps, and a digit line contact between opposing substantially vertical surfaces of the semiconductive material, between opposing substantially vertical surfaces of the insulating material, adjacent to substantially horizontal surfaces of the word line caps, and between opposing substantially vertical surfaces of the word line caps. A transition surface extending between and connecting the substantially horizontal surface and the substantially vertical surface of the respective word line caps projects toward a longitudinal axis extending centrally through the digit line contact. Methods of forming the semiconductor device are also disclosed, as are electronic systems including the semiconductor device.