3D NAND Digit Line Offset and Multiplexer Architecture
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Solution Overview
Problem
Conventional 3D NAND Flash memory devices face limitations in performance and feature size reduction due to the configuration of digit lines and logic circuitry, which hinder data transfer rates and increase power consumption.
Innovation Solution
The microelectronic device structure incorporates a configuration where first and second digit lines are horizontally offset and terminated within an additional region, with multiplexer devices coupled to both, allowing for reduced lengths and enhanced performance by facilitating faster data transfer and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional digit lines and logic circuitry are used in 3D NAND Flash memory devices, then the device can be fabricated with existing processes, but data transfer rates are limited and power consumption increases
Solution Approach 1:
The patent transitions from conventional planar digit line arrangements to a three-dimensional architecture where digit lines are vertically stacked and interconnected through multiple levels. This dimensional change allows shorter horizontal digit line lengths while maintaining connectivity to all memory strings, thereby increasing data transfer rates and reducing power consumption without sacrificing access capability.
Solution Approach 2:
The digit line system is segmented into multiple independent segments at different vertical levels, with each segment serving specific memory regions. This segmentation allows parallel data transfer operations across multiple segments simultaneously, increasing overall data transfer rate while reducing the burden on individual digit lines, thus lowering power consumption.
2Area of stationary object
If digit line contacts are provided at openings next to edges of the vertical memory array, then connections to logic circuitry are established, but the horizontal footprint and device size increase
Solution Approach 1:
The patent moves digit line contacts from the horizontal plane (edge openings) to the vertical dimension by implementing through-silicon vias and vertical interconnect structures. This allows digit line contacts to be distributed across multiple vertical levels within the memory array, reducing the need for large peripheral opening areas while maintaining reliable electrical connections to logic circuitry.
Solution Approach 2:
The patent merges the functions of digit line contacts, select gate contacts, and other interconnect elements by integrating them into shared vertical via structures and common contact regions. This consolidation reduces the total area required for all contact openings while ensuring that each digit line maintains its reliable connection path to the logic circuitry through the integrated interconnect system.
3Quantity of substance
If vertical memory array architectures are used to increase memory density, then more memory cells fit in a unit die area, but conventional digit line configurations hamper performance improvements and size reductions
Solution Approach 1:
The patent implements a multi-level digit line architecture where digit lines are arranged in vertical stacks with interconnect structures enabling horizontal and vertical routing. This three-dimensional digit line configuration maintains short horizontal distances to all memory strings while accommodating the high density of vertically stacked memory cells, thereby achieving both high memory density and fast data transfer rates simultaneously.
Solution Approach 2:
The high-density memory array is divided into multiple banks or regions, each served by dedicated digit line segments at different vertical levels. This segmentation allows parallel access to multiple memory regions through independent digit line segments, increasing data transfer rate while maintaining the high overall memory density achieved through vertical stacking.
Data Source
AI summary
A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.