Digit-Recurrence Selection Constants for Square Root and Divide
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Solution Overview
Problem
Existing digit recurrence algorithms face challenges in balancing performance, circuit area, and power consumption when implementing higher radix operations for square root and divide operations, particularly in meeting timing requirements for fitting multiple sub-iterations within a single processing cycle.
Innovation Solution
The approach involves splitting a higher-radix iteration into multiple lower-radix sub-iterations within the same processing cycle, using shared circuitry and speculative replication to reduce timing delays and circuit complexity, and employing on-the-fly conversion to efficiently handle redundant and non-redundant representations of remainder values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a higher radix is used in digit recurrence algorithm, then the number of iterations is reduced and performance is improved, but the circuit complexity and power consumption increase
Solution Approach 1:
The patent divides a higher-radix iteration into multiple lower-radix sub-iterations. For example, a radix-16 iteration is segmented into two radix-8 sub-iterations, each handling a portion of the result bits. This segmentation reduces the complexity of individual iteration circuits while maintaining the performance benefit of processing multiple bits per iteration cycle.
Solution Approach 2:
The patent dynamically selects between different radix configurations based on operational requirements. The system can adaptively choose to perform full higher-radix iterations when performance is critical or switch to segmented lower-radix sub-iterations when circuit resource constraints exist, enabling flexible optimization of the performance-complexity tradeoff.
2Productivity
If a higher radix is used in digit recurrence algorithm, then fewer iterations are needed, but the area of circuitry required increases
Solution Approach 1:
By segmenting a radix-16 iteration into two radix-8 sub-iterations, the patent reduces the circuit area required for each iteration stage. Each sub-iteration uses smaller comparison circuits and selection logic, fitting within available circuit area constraints while still achieving 2 bits of result per iteration cycle through the combined sub-iterations.
Solution Approach 2:
The patent uses speculative replication of circuitry for the sub-iterations, where identical comparison and selection circuits are copied and configured for different radix values. This allows the same physical circuit block to be reused for both radix-8 and radix-16 operations, optimizing area utilization.
3Productivity
If a higher radix is used in digit recurrence algorithm, then performance is improved, but power consumption increases
Solution Approach 1:
Segmenting higher-radix iterations into lower-radix sub-iterations reduces power consumption by activating only the necessary comparison and selection circuits for each sub-iteration. For example, performing two radix-8 sub-iterations activates fewer logic gates simultaneously than a single radix-16 iteration, reducing dynamic power consumption while maintaining the same processing throughput.
Solution Approach 2:
The system dynamically configures the radix and number of sub-iterations based on power availability and performance requirements. When power consumption needs to be reduced, the system can opt for segmented sub-iterations with lower switching activity, while still achieving acceptable performance levels.
4Productivity
If multiple sub-iterations are fitted within a single processing cycle, then performance is improved, but timing requirements become more difficult to meet
Solution Approach 1:
The patent segments the iteration logic into distinct, modular sub-iteration stages that can be pipelined or executed sequentially within a cycle. Each sub-iteration stage has well-defined input and output interfaces, making timing analysis and synchronization easier. The segmented structure allows for systematic timing closure by optimizing each stage independently.
Solution Approach 2:
The patent performs preliminary setup of comparison constants and selection logic before each sub-iteration begins. Selection constants for the next sub-iteration are pre-computed and loaded into lookup tables in advance, reducing the critical path delay during the actual sub-iteration execution and making it easier to meet tight timing requirements.
Data Source
AI summary
A data processing apparatus to perform a digit-recurrence operation on an input value comprises receiver circuitry for receiving a remainder value of a previous iteration of the digit-recurrence operation. Comparison circuitry performs comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation and outputs the next digit of the result of the digit-recurrence operation based on the comparisons. Each of the selection constants is associated with one of the available digits and an input parameter. Storage circuitry stores a subset of the selection constants, the subset of the selection constants excluding an excluded selection constant from the selection constants, which is associated with an excluded digit from the available digits.