Digit-Serial MAC Accelerator Zero-Digit Gating
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Deep convolutional neural networks (DCNNs) require efficient hardware accelerators to perform computationally expensive operations like convolutions and dot products, which are power-intensive and costly when using general-purpose hardware, especially in mobile and consumer electronics where real-time constraints and power consumption are concerns.
Innovation Solution
A digit-serial Multiply Accumulate (MAC) hardware accelerator is developed, integrating digit-serial architectures within a bit-parallel stream-computation framework, using word-level unfolding techniques to adapt the architecture and eliminate input parallel-to-serial converters, and incorporating pre-processing logic for gating multipliers based on zero-value digit detection to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If general-purpose hardware is used to perform DCNN operations, then computational flexibility is maintained, but power consumption increases and processing speed decreases
Solution Approach 1:
The hardware accelerator is segmented into specialized functional units including digit-serial multipliers, accumulation units, and gating circuits that process DCNN operations in a divided, modular manner. This segmentation allows each unit to be optimized for specific computational tasks, achieving high throughput while maintaining low power consumption through efficient resource utilization.
2Area of stationary object
If digit-serial architecture is used in MAC hardware accelerators, then area occupation is reduced, but computational throughput may be affected
Solution Approach 1:
The digit-serial architecture employs periodic clock gating where multipliers are activated only during specific clock cycles when non-zero digits are present. This periodic action pattern allows the hardware to process data serially over time rather than requiring all multipliers to be active simultaneously, significantly reducing area occupation while maintaining computational throughput through time-multiplexed operation.
Solution Approach 2:
The system dynamically adjusts the operation of multipliers based on the actual data being processed. Pre-processing logic analyzes input digits and dynamically gates multipliers to operate only when needed, transforming a static hardware configuration into a dynamic system that adapts to data characteristics, thereby optimizing both area usage and throughput.
3Loss of energy
If pre-processing logic with gating circuits is added to control multipliers, then power consumption is reduced, but device complexity increases
Solution Approach 1:
Pre-processing logic is implemented to analyze input digits and generate gating control signals before the main multiplication operation occurs. This preliminary action identifies which multipliers need to be activated and prepares control signals in advance, allowing the main computational units to operate efficiently without unnecessary switching activity, thereby reducing power consumption while keeping the added complexity minimal and localized to the control logic.
Data Source
AI summary
A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.