Digit-Serial Squaring Circuit for Low-Power Cryptography
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing squaring circuit architectures face challenges in efficiently computing the square of a fixed-point value, particularly in digital signal processing and cryptography applications, where they often require high-speed and low-power operations while managing increasing demands for cryptography hardware support in mobile devices.
Innovation Solution
A digit-serial squaring technique is introduced, which iteratively computes the square of a fixed-point value by decatenating substrings of a specified size, allowing for a trade-off between bit-serial and parallel architectures, and efficiently implements the computation using a radix-β number system, where β=2m, to produce 2m bits of the result in each iterative step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional parallel squaring circuit architectures are used, then computation speed is improved, but circuit area and complexity increase
Solution Approach 1:
The fixed-point value is divided into substrings of specified size, and the squaring operation is performed iteratively on these substrings. This segmentation allows the circuit to process smaller data segments sequentially, reducing the required circuit area while maintaining acceptable computation speed through the iterative approach.
Solution Approach 2:
The circuit uses an iterative computation approach where the operand is dynamically updated in each iteration by decatenating the previous operand's least significant bits equal to the substring size. This dynamic updating allows the same circuit structure to process different data segments over time, reducing hardware requirements compared to a fully parallel architecture.
2Area of stationary object
If iterative digit-serial squaring technique is used, then circuit area is reduced, but computation time increases
Solution Approach 1:
The circuit allows trading off between substring size and computation iterations. By adjusting the substring size parameter, designers can optimize the balance between circuit area (smaller substrings reduce area) and computation time (smaller substrings require more iterations). This parameter adjustment provides flexibility to meet different performance requirements.
Solution Approach 2:
The squaring operation is performed through periodic iterative steps, where each iteration processes a substring and updates the operand. This periodic action breaks down the computation into manageable stages, allowing the circuit to achieve the desired functionality with reduced hardware resources while distributing the computational workload over multiple clock cycles.
3Productivity
If larger substring size is used, then fewer iterations are needed, but circuit complexity increases
Solution Approach 1:
The circuit pre-determines the substring size and prepares the operand by identifying the least significant bits equal to the substring size before each squaring operation. This preliminary preparation simplifies the iterative process by ensuring the data is in the correct format, reducing the complexity of the squaring logic itself while maintaining efficient iteration throughput.
Data Source
AI summary
Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fixed-point value equal to the substring size.