Digital Audio Rate Conversion Using Jitter Noise Reduction

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Solution Overview

Problem

Conventional methods for wireless audio applications face challenges in handling frequency mismatches between device clocks, leading to high power consumption and costs due to the need for complex digital filter designs or additional analog circuitry.

Innovation Solution

A fully digital audio conversion method that generates a second sampling rate by selecting clock cycles closest to the first sampling rate, correcting for sampling frequency and jitter errors using interpolation, thereby avoiding costly analog components and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If complex digital filter designs are used to maintain sufficient SNR for high-fidelity audio applications, then audio quality is improved, but power consumption and computing resources increase significantly

Engineering Contradiction:

Improveaudio qualityVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent changes the approach from using complex high-order digital filters to using simpler filters combined with dithering techniques. By modifying the signal processing parameters and adding controlled noise (dither), the system achieves the required SNR performance with significantly reduced computational complexity and power consumption on DSP processors

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces dither noise as an intermediary element that facilitates the use of simpler digital filters. The dither signal acts as a mediator that prevents distortion and maintains audio quality when using lower-complexity filtering approaches, thereby reducing the power consumption burden while preserving high-fidelity audio output

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If separate analog phase-locked loop circuitry is used to adjust clock rates, then clock synchronization is improved, but device complexity and cost increase

Engineering Contradiction:

Improveclock synchronizationVSAvoidanalog circuitry

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical/analog phase-locked loop circuitry with a fully digital clock rate adjustment mechanism. By using digital signal processing techniques to generate and adjust clock rates, the system achieves the same synchronization functionality without requiring additional analog components, thereby reducing device complexity and cost while maintaining reliable clock synchronization

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent integrates clock rate adjustment functionality into the existing digital signal processing architecture, allowing the same digital processing units to handle both audio signal processing and clock synchronization tasks. This multi-functional approach eliminates the need for separate dedicated analog phase-locked loop circuits, reducing overall device complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250006216A1Systems and methods for low-power fully digital rate conversion using pre- or post- jitter noise reduction

Publication Date: 2025.01.02 QORVO US INC

AI summary

A method for digital audio conversion is provided. The method includes receiving, at a first sampling rate, a digital audio data stream at a device. The method includes generating, by a clock connected to the device, a second sampling rate, wherein the second sampling rate approximates the first sampling rate by selecting cycles of the clock closest to the cycles of the first sampling rate. The method also includes sampling the digital audio data stream at the second sampling rate to generate a second audio data stream. The method further includes transmitting the second audio data stream to a codec.