Digital BFSK Modulation Using Intermediate Clock Phase Selection
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Solution Overview
Problem
Existing binary frequency shift keying (BFSK) modulation technologies for USB Power Delivery (USBPD) face challenges such as excessive architectural complexity, high power consumption, and difficulties in meeting eye diagram compliance, especially at high data rates, due to harmonics and complex filtering requirements.
Innovation Solution
The implementation of BFSK modulation by generating a modulated intermediate clock frequency using appropriate phases of a high frequency clock, which is then used to create pulse width modulated phases for synthesizing a sine waveform with suppressed lower harmonics, allowing for digital domain modulation and reduced analog circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If square wave-to-triangle wave-to-class A driver architecture is used, then implementation is conceptually simple, but harmonics are introduced requiring complex on-chip filtering and high operating current
Solution Approach 1:
The patent extracts and removes the problematic harmonics generated by the square wave-to-triangle wave conversion through carefully designed current mirror circuits and timing control. By taking out the harmful harmonic components while retaining the fundamental frequency, the system achieves simple implementation without requiring complex filtering circuits.
Solution Approach 2:
The patent converts the harmful harmonics generated by the class A driver into a beneficial timing reference signal. The harmonic-rich square wave is used to drive current mirrors that generate precisely timed current pulses, transforming what would be noise into a useful synchronization mechanism for the BFSK modulation.
2Ease of manufacture
If direct digital synthesis architecture is used, then implementation is simple and testing is facilitated, but power consumption increases and circuit area expands
Solution Approach 1:
The patent replaces the mechanical/digital direct digital synthesis approach with an analog-based solution using current mirrors and timing-controlled switches. This substitution achieves BFSK modulation with significantly reduced power consumption and circuit area while maintaining implementation simplicity and testability.
3Ease of manufacture
If PLL loop modulation architecture is used, then implementation is conceptually simple and suitable for low data rate switching, but difficulty arises in meeting eye diagram at USBPD-compliant data rate
Solution Approach 1:
The patent employs periodic action by using precisely timed current pulses that occur at specific phases of the carrier wave. The timing control circuit generates periodic current switches that modulate the carrier frequency, achieving clean eye diagrams at USBPD data rates without requiring complex PLL bandwidth control.
4Productivity
If PLL loop modulation is used for USBPD data rate, then low data rate switching is achieved, but considerable time is required for design, test and calibration
Solution Approach 1:
The patent implements preliminary action by pre-calculating and hardcoding the optimal timing phases for BFSK modulation in the timing control circuit. The current mirror ratios and switch timing are designed beforehand to directly achieve USBPD compliance, eliminating the need for extensive post-manufacturing calibration and reducing design iteration time.
Data Source
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AI summary
In described examples, binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock (40) to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency, and M is an integer. Depending on the binary data "1" or "0" to be transmitted (45), "M" or "M+l" clock phases from the high frequency clock are converted (43) to an intermediate clock (44) that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock (44), generated entirely in the digital domain, has the required data modulation in it, and is used for generating (46) N pulse width modulated (PWM) phases (47) of waveforms operating at the carrier frequency. The N phases (47) are then weighed appropriately (48) to synthesize a sine waveform (49) whose lower harmonics are substantially suppressed.