Programmable Digital Blocks Control Analog Routing
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Solution Overview
Problem
Conventional integrated circuit devices face performance limitations, particularly at high sample frequencies, due to CPU resource consumption, increased response latency, and high power consumption, when using successive approximation register type digital-to-analog converters (SARDACs), which require complex configuration and additional memory resources.
Innovation Solution
The integration of programmable digital blocks and a dedicated sequencer circuit allows for independent configuration and control of fixed-function analog circuits, such as ADCs, reducing CPU load and enabling flexible signal routing without relying on processor resources, thereby enhancing performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CPU is used to control SARDAC at high sample frequencies, then conversion functionality is achieved, but CPU resource consumption increases and other tasks cannot be completed
Solution Approach 1:
The patent segments the control functionality by introducing a dedicated sequencer circuit that handles SARDAC control independently from the CPU. The sequencer is divided into multiple stages (first sequencer stage for initial conversion, second sequencer stage for subsequent conversions) that can operate autonomously at high frequencies without burdening the CPU, thus resolving the contradiction between high sample frequency and CPU task completion capability
Solution Approach 2:
The patent introduces a sequencer circuit as an intermediary between the CPU and SARDAC. This intermediary handles the high-frequency control operations, allowing the CPU to remain available for other tasks while the sequencer manages the demanding SARDAC control requirements at high sample frequencies
2Speed
If CPU is used to control SARDAC, then conversion operations are performed, but response latency increases
Solution Approach 1:
The patent implements preliminary action by having the sequencer pre-configured and ready to immediately control SARDAC conversions without CPU intervention. The sequencer can autonomously manage conversion sequences, eliminating the time delay that would occur if the CPU had to handle each conversion request, thus reducing response latency while maintaining high conversion speed
3Speed
If CPU is used to control SARDAC at high frequencies, then high sample frequency is achieved, but power consumption increases
Solution Approach 1:
The patent segments the power-consuming control functions by moving SARDAC control from the CPU to a dedicated sequencer circuit. This segmentation allows high-frequency sampling to be performed by the low-power sequencer rather than the high-power CPU, achieving high sample frequency while significantly reducing overall power consumption
4Speed
If SARDAC is configured to respond to high frequencies, then high sample frequency is achieved, but configuration complexity and memory resources increase
Solution Approach 1:
The patent implements self-service by designing the sequencer circuit to autonomously manage SARDAC configuration and control without requiring complex CPU-based configuration code. The sequencer contains built-in logic to handle high-frequency operations, eliminating the need for complex firmware and additional memory resources while achieving high sample frequency
Data Source
AI summary
An integrated circuit device can include a plurality of analog blocks, including a plurality of programmable analog blocks configurable to provide different analog functions in response to configuration data, at least one programmable analog block including a programmable analog routing coupled to a plurality of external connections to the integrated circuit device; and a plurality of programmable digital blocks, at least one programmable digital block configurable into an analog block control circuit that configures the programmable analog routing.