Digital Buffer PLL Jitter Control for Memory Systems
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Solution Overview
Problem
Current digital data buffers fail to optimize setup/hold timing relationships and are susceptible to phase jitter, especially at high clock frequencies above 800 MHz, making them unsuitable for advanced memory systems.
Innovation Solution
A digital data buffer with a phase-locked loop (PLL) and a double buffer structure using flip-flops to provide a jitter-cleaned clock signal and maintain optimal timing margins, featuring an external feedback loop for temperature stability and low phase variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional digital data buffer is used, then the device complexity is low, but the setup/hold timing relationship is not optimized and phase jitter occurs at high clock frequencies
Solution Approach 1:
The buffer is divided into multiple independent data paths, each with its own flip-flops and timing control. This segmentation allows each path to be independently optimized for timing relationships while maintaining overall system functionality, resolving the contradiction between reliability and complexity.
Solution Approach 2:
A phase-locked loop (PLL) with feedback mechanism is implemented to continuously monitor and adjust clock signal timing. The feedback loop ensures optimal setup/hold timing relationships are maintained even at high clock frequencies, achieving reliability improvement despite increased device complexity.
2Productivity
If the clock frequency is increased to above 800 MHz, then the productivity of the memory system is improved, but phase jitter increases and timing margins deteriorate
Solution Approach 1:
The PLL uses feedback control to lock onto the clock frequency and maintain stable phase relationships even at high frequencies above 800 MHz. This allows the system to achieve high productivity while maintaining phase stability through continuous automatic adjustment.
Solution Approach 2:
The system dynamically adjusts timing parameters and phase relationships through the PLL mechanism to maintain optimal performance at different clock frequencies. This parameter adjustment capability enables high-frequency operation without sacrificing phase stability.
3Stability of the object's composition
If a simple buffer structure is used, then the device complexity is low, but temperature variations cause phase variations and timing margin degradation
Solution Approach 1:
The feedback mechanism in the PLL continuously compensates for temperature-induced phase variations by adjusting timing parameters in real-time. This feedback control maintains timing margin stability across temperature variations without requiring an overly complex buffer architecture.
Solution Approach 2:
The system automatically adjusts timing parameters in response to temperature changes through the PLL mechanism, maintaining stable timing margins despite environmental variations. This dynamic parameter adjustment achieves temperature compensation without excessive structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures a maximum, temperature-stable setup/hold timing margin and minimizes propagation delay, effectively handling high-frequency clock signals while maintaining signal integrity in memory systems.
Implementation Method 1
A second clock output of the phase-locked loop provides a clock signal (PDCLK) shifted in phase by a fraction (X) of the clock period with respect to the feedback clock signal (PFBCLK) for application to the clock input of the second data register (FF2)
Implementation Method 2
A third clock output of the phase-locked loop provides a clock signal (PQCLK) shifted in phase by an amount of 180° plus a fraction (X; Z) of the clock period with respect to the feedback clock signal (PFBCLK) for application to the clock input of the data destination device
Data Source
AI summary
A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for application to a data destination device such as memory devices. The buffer further has a clock output for providing an output clock signal (QCLK) to the data destination device and a phase-locked loop (PLL) with a clock input, a feedback input, a feedback output and a plurality of clock outputs. The buffer uses a pair of data registers, i.e. flip-flops (FF1, FF2) connected in series in each data path. The first data register in each data path is clocked by the clock input signal (CLK) and the second data register in each data path is clocked by one of the clock outputs (PDCLK) from the PLL.