Digital Capacitance Converter Using Iterative Delay Discharge
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Solution Overview
Problem
Conventional capacitance-to-digital converters often rely on analog/mixed-signal circuits, which occupy significant area and are not easily migratable to new technologies, limiting their resolution and efficiency in applications like capacitive pressure sensors, touch sensors, and fluid level detectors.
Innovation Solution
A fully digital capacitance-to-digital converter employing iterative delay-chain discharging, utilizing a first and second delay block with a capacitance determination unit that calculates capacitance based on time differences and clock periods, enhancing resolution through a time-to-digital converter and counter module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog/mixed-signal circuits are used for capacitance-to-digital conversion, then conversion capability is achieved, but area occupation increases and technology migrability decreases
Solution Approach 1:
The patent replaces analog/mixed-signal circuits with a fully digital implementation using delay blocks, counters, and digital logic. The capacitance measurement is converted to a digital value through iterative discharge cycles controlled by digital counters, eliminating the need for analog components and enabling standard CMOS fabrication.
Solution Approach 2:
The conversion process is segmented into discrete digital steps: charging the capacitor, iterative discharging through delay blocks, counting discharge cycles, and calculating the final value. This segmentation enables the use of simple digital components rather than complex analog circuits.
2Measurement precision
If analog/mixed-signal circuits are used for capacitance-to-digital conversion, then conversion capability is achieved, but adaptability to new technologies decreases
Solution Approach 1:
The patent replaces analog/mixed-signal circuits with a fully digital implementation using delay blocks, counters, and digital logic. The capacitance measurement is converted to a digital value through iterative discharge cycles controlled by digital counters, eliminating the need for analog components and enabling standard CMOS fabrication.
3Area of stationary object
If iterative delay-chain discharging is used, then area efficiency is improved, but measurement resolution may be reduced
Solution Approach 1:
The patent uses dynamic timing adjustment where the delay block's delay time varies with the capacitor voltage during iterative discharge. The measurement resolution is enhanced by capturing the exact timing when the delay output transitions, providing fine-grained measurement capability within a compact digital structure.
Solution Approach 2:
The patent introduces a time-to-digital converter as an intermediary that measures the precise timing of signal transitions with high resolution. This TDC unit acts as a mediator between the coarse iterative discharge process and the final high-resolution capacitance value, enabling accurate measurement without requiring large analog components.
Data Source
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AI summary
A capacitance-to-digital-converter comprising: a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.