Digital CDR Architecture for LVDS Video Transceivers
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Solution Overview
Problem
Conventional Low-Voltage Differential Signaling (LVDS) video transceivers face challenges in tolerating delay skewing between channels and timing jitter, especially at high frequencies, which affects the precision of Clock and Data Recovery (CDR) circuits, particularly during video blanking periods.
Innovation Solution
A fully digital clock and data recovery architecture that uses a shared Phase-Locked Loop (PLL) to generate multi-phase clock signals, allowing for independent tracking of clock and data channels, and employs blind oversampling algorithms to adjust the initial sampling point and ensure maximal skew tolerance, thereby improving synchronization and phase tracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay-locked loop (DLL) circuit is used for timing recovery on the clock link, then timing synchronization is achieved, but the precision is insufficient at high frequencies and cannot tolerate both delay mismatch and timing jitter
Solution Approach 1:
The invention segments the timing recovery function into two independent parts: clock link timing recovery (using DLL) and data link timing recovery (using separate CDR circuits). This segmentation allows each part to be optimized independently - the DLL provides coarse timing synchronization while the data CDR circuits provide fine timing adjustment and jitter tolerance, resolving the contradiction between precision and reliability.
Solution Approach 2:
The invention introduces an intermediary mechanism where the clock CDR circuit's output serves as a reference for multiple data CDR circuits. This intermediary approach allows timing information to be propagated from the clock link through intermediate CDR stages to the data links, enabling each data CDR to independently track and compensate for timing variations, thus achieving both precision and reliability.
2Device complexity
If timing recovery is performed only on the clock link using DLL, then system complexity is reduced, but skew tolerance between channels is insufficient
Solution Approach 1:
The invention segments the CDR functionality into a dedicated clock CDR circuit and multiple data CDR circuits. The clock CDR recovers timing from the clock link and provides a reference for data CDRs, which independently recover timing for their respective data links. This segmentation enables each data CDR to tolerate channel-specific skew while maintaining overall system synchronization, achieving high skew tolerance without excessive complexity.
Solution Approach 2:
The clock CDR circuit performs preliminary timing recovery by locking to the clock link first and generating a stable reference clock signal. This preliminary action establishes a common timing baseline before data CDR circuits perform their own timing recovery on individual data links, allowing them to compensate for skew relative to this baseline while maintaining manageable overall system complexity.
3Reliability
If conventional CDR circuits are used, then basic data recovery is achieved, but performance degrades during video blanking periods under spread-spectrum modulation
Solution Approach 1:
The data CDR circuits implement feedback mechanisms that continuously monitor data transitions and adjust timing accordingly. During active video periods, the feedback tracks data transitions to maintain synchronization. During blanking periods when no data transitions occur, the feedback holds the last known good timing state, preventing loss of lock and enabling seamless resumption of tracking when video data returns, thus maintaining reliability while simplifying operation during blanking.
Data Source
AI summary
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.