Digital CDR Circuit Using TDCs for Jitter-Tolerant Clock Recovery
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Solution Overview
Problem
Conventional phase locked loop (PLL) or delay locked loop (DLL)-based clock and data recovery circuits struggle with jitter, frequency drift, and ground shifting in USB Type-C communication, making it difficult for receivers to recover the clock and retime data effectively without a reference clock.
Innovation Solution
A clock and data recovery circuit using time-to-data converters (TDCs) and a digitally controlled oscillator (DCO) to generate a recovery clock signal, with a processing circuit that filters and adjusts the oversampled data to account for phase tracking and jitter, allowing for asynchronous reset and operation without a reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL or DLL-based CDR is used, then clock recovery can be achieved with reference clock, but it cannot work properly without reference clock and cannot handle fast events like cycle-to-cycle jitter and fast frequency drift
Solution Approach 1:
The patent replaces conventional mechanical PLL/DLL systems with a digital CDR system using TDCs and DCO. This digital approach eliminates the need for external reference clocks and provides fast phase tracking capability by directly measuring time intervals and generating digital control signals for frequency and phase adjustment.
Solution Approach 2:
The patent dynamically changes the operating parameters of the DCO based on feedback from TDC measurements. By continuously adjusting the DCO frequency and phase according to measured time intervals and detected edges, the system adapts to fast frequency drift and cycle-to-cycle jitter without requiring a stable reference clock.
2Productivity
If general-purpose receiver is used, then instruction speed and low power are achieved, but it cannot provide USB Type-C reference clock and cannot properly recover clock and retime data
Solution Approach 1:
The patent implements a multi-functional receiver circuit that combines general-purpose data reception with specialized clock recovery and data retiming capabilities. The circuit integrates TDCs for time measurement, DCO for frequency generation, and filtering mechanisms to handle both instruction data and USB Type-C formatted data, enabling it to serve multiple functions simultaneously.
3Reliability
If conventional CDR is used, then basic clock recovery is possible, but it does not have fast phase track capability and is affected by ground shifting
Solution Approach 1:
The patent performs preliminary actions by continuously measuring time intervals and detecting edges in the incoming data stream before final clock recovery is complete. The TDCs continuously track time differences and the DCO pre-adjusts frequency based on these measurements, enabling fast phase tracking when changes occur without waiting for conventional locking procedures.
Data Source
AI summary
In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.