Digital CDS Circuit Using Gray Code for Accurate CMOS Image Sensing

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Solution Overview

Problem

Correlated double sampling (CDS) technologies in CMOS image sensors face challenges in compensating for variations in analog pixel signals due to fixed pattern noise and differences in ADC converters, leading to inaccuracies in digital pixel signals.

Innovation Solution

A digital CDS circuit comprising a first latch unit, a second latch unit, and a calculating unit that stores and processes digital reset and image component data using Gray codes, performing XOR operations to generate effective image data, thereby simplifying the structure and reducing size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If digital CDS circuit uses traditional binary code processing, then calculation accuracy is maintained, but circuit complexity and size increase

Engineering Contradiction:

Improvecircuit structureVSAvoidsignal processing accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent changes the number system parameter from binary code to Gray code for representing digital signal data. This parameter change allows the use of simpler XOR operations instead of complex subtraction circuits, reducing circuit complexity while maintaining the ability to accurately process and compensate signal variations through the properties of Gray code representation

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent substitutes complex digital subtraction logic with simpler XOR gate operations. By using Gray code representation, the complicated borrow-carry logic of binary subtraction is replaced with parallel XOR operations, significantly simplifying the calculating unit structure while preserving the correlated double sampling function

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Speed

If digital CDS circuit processes all bits simultaneously, then processing speed is improved, but circuit complexity increases

Engineering Contradiction:

Improvedata processing speedVSAvoidcircuit structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent segments the digital data into individual bits processed through separate latch units (first latch unit for image component data, second latch unit for reset component data). Each latch unit processes bits independently using simple XOR operations, allowing parallel processing that improves speed while keeping each individual processing element simple in structure

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9380246B2Digital correlated double sampling circuit and image sensor including the same

Publication Date: 2016.06.28 SAMSUNG ELECTRONICS CO LTD

AI summary

A digital correlated double sampling (CDS) circuit includes a first latch unit, a second latch unit and a calculating unit. The first latch unit stores digital reset component data and digital image component data by latching a count signal in response to a first control signal. The second latch unit stores the digital reset component data by latching an output of the first latch unit in response to a second control signal. The calculating unit generates digital effective image data by subtracting the digital reset component data from the digital image component data.