Digital Correlated Double Sampling Circuit for CMOS Image Sensors
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Solution Overview
Problem
Correlated double sampling (CDS) technologies in CMOS image sensors face challenges in reducing quantization noise and increasing the number of effective bits without increasing the number of bits in the count signal, due to variations in pixel characteristics and analog-to-digital converter characteristics.
Innovation Solution
A digital CDS circuit is implemented with a first and second latch circuit, a decision circuit, a delay control circuit, and a calculating circuit, which stores reset and image component data based on comparison signals and generates effective image data by subtracting reset component data from image component data, allowing for reduced quantization noise and increased effective bits without increasing the count signal bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits of the count signal is increased to increase the number of effective bits, then the number of effective bits is improved, but the device complexity and processing overhead increase
Solution Approach 1:
The patent segments the sampling process into two distinct intervals: reset interval and image interval. By separating the sampling of reset component data and image component data into different time periods, the system achieves correlated double sampling without requiring additional bits in the count signal, thus improving measurement precision while avoiding increased device complexity
Solution Approach 2:
The patent performs preliminary sampling of reset component data during the reset interval before the image interval. This preliminary action allows the system to capture and store reset component data (including fixed pattern noise) in advance, which is then subtracted from the image component data to eliminate noise and improve the number of effective bits without increasing count signal bits
2Measurement precision
If digital CDS is implemented to reduce quantization noise, then quantization noise is reduced, but the device complexity increases due to additional circuits
Solution Approach 1:
The patent merges the CDS function into the existing digital pipeline by utilizing the count signal and comparison signals that are already generated by the ADC and comparator circuits. By combining the reset interval sampling and image interval sampling operations within the existing digital infrastructure, the system reduces quantization noise without requiring separate dedicated CDS hardware circuits
Solution Approach 2:
The count signal and comparison signals serve multiple functions: they are used for both analog-to-digital conversion and for correlated double sampling operations. This multi-functionality allows the system to achieve quantization noise reduction through digital CDS without adding dedicated single-purpose circuits, thereby reducing device complexity
Data Source
AI summary
A digital correlated double sampling circuit includes a first latch circuit, a second latch circuit, a decision circuit, a delay control circuit and a calculating circuit. The first latch circuit stores first reset component data. The second latch circuit stores second reset component data and stores image component data based on a selected comparison signal during an image interval. The decision circuit outputs a decision signal by determining identity of the first reset component data and the second reset component data during the reset interval. The delay control circuit outputs the reset comparison signal and outputs one of the first image comparison signal and the second comparison signal as the selected comparison signal. The calculating circuit generates effective image data by subtracting the second reset component data from the image component data and sequentially outputs the effective image data.