Digital CDS Circuit for High-Speed Low-Power Image Sensors
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Solution Overview
Problem
CMOS image sensors face challenges in high-speed operation due to variations in analog pixel signals and power consumption, which are not effectively addressed by existing correlated double sampling (CDS) technologies.
Innovation Solution
A digital CDS circuit comprising a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit, which converts phase shift codes into Gray codes and then binary codes to subtract reset components from image components, thereby generating effective image components with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CDS technologies are used to compensate signal variations, then measurement precision is improved, but power consumption increases at high frame rates
Solution Approach 1:
The patent replaces the conventional analog CDS circuit with a digital CDS circuit that operates on digital pixel signals. This substitution fundamentally changes the operating domain from analog to digital, allowing the system to maintain signal variation compensation capabilities while operating at higher frequencies with reduced power consumption, as digital circuits can be optimized for low-power high-speed operation
Solution Approach 2:
The patent changes the operating parameters by processing digital pixel signals instead of analog signals. This parameter change enables the CDS operation to be performed in the digital domain where power consumption can be better controlled at high frame rates, resolving the contradiction between maintaining measurement precision and reducing power consumption
2Productivity
If frame rates and operating frequencies are increased to improve productivity, then output per unit time is improved, but power consumption increases
Solution Approach 1:
By substituting analog signal processing with digital signal processing, the system achieves better scalability to high frame rates. Digital circuits can be designed with optimized clocking and power management that allows high-speed operation without the proportional power increase seen in analog systems, thus improving productivity while controlling power consumption
Data Source
AI summary
A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.


