Digital-to-Charge Converter Feedback for Low-Power Analog Output
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) are not suitable for low-power applications as they consume significant power due to constant operation, whereas Pulse Width Modulator (PWM) circuits also dissipate power constantly and wake up frequently, leading to inefficient power management.
Innovation Solution
A digital-to-charge converter (DQC) system that includes a converting circuit to determine the charge on a capacitor, an error determining circuit to calculate the difference between target and present charge, and a correction circuit to control a programmable current source to adjust the charge, allowing the system to operate in low-power modes by minimizing active time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional DAC is used to convert digital signal to analog signal, then the analog signal output is directly proportional to the digital input value, but the device consumes significant power due to constant operation
Solution Approach 1:
The patent implements periodic sampling of the capacitor voltage at discrete time intervals instead of continuous operation. The DAC converts digital values to analog voltages only when needed for charging the capacitor, allowing the system to enter low-power states between conversions. This periodic action maintains the required analog signal accuracy while dramatically reducing average power consumption compared to continuous DAC operation.
2Use of energy by moving object
If a PWM circuit is used to replace DAC in low-power applications, then power consumption is reduced, but the controller must wake up at twice the PWM frequency consuming significant power
Solution Approach 1:
The patent implements a feedback mechanism where the ADC continuously monitors the capacitor voltage and compares it against a target voltage. Based on this feedback, the system determines when charging is needed and for how long. This feedback loop allows the controller to remain in sleep mode longer and only wake up when the capacitor voltage deviates from the target, significantly reducing the frequency and duration of wake-up events compared to PWM-based solutions.
Solution Approach 2:
The system pre-charges the capacitor to a target voltage level before the actual conversion operation. By establishing this preliminary charge state, the system can extend the time between active operations and only intervene when the voltage drops below the target threshold. This preliminary action reduces the frequency of controller wake-ups and extends sleep duration.
3Use of energy by moving object
If the controller toggles voltage during active state and sleeps between toggle times in PWM circuit, then low-power operation is achieved, but the controller wakes up at twice the PWM frequency consuming significant power
Solution Approach 1:
The patent implements dynamic adjustment of the charging duration based on the difference between the measured voltage and the target voltage. The charging time is dynamically calculated to be just long enough to reach the target voltage, avoiding unnecessary extended active periods. This dynamic approach optimizes the balance between conversion speed and power consumption, allowing faster conversions when voltage deviation is large while extending sleep time when the target voltage is already接近.
Data Source
AI summary
Systems and methods for a digital-to-charge converter (“DQC”) are disclosed. A DQC may include a converting circuit configured to receive a first digital signal indicative of a voltage across a capacitor coupled to an output pin of the digital-to-charge converter and to determine a present charge of the capacitor based at least in part on the first digital signal. The DQC may also include an error determining circuit coupled to the converting circuit, wherein the error determining circuit is configured to receive a second digital signal indicative of a target charge via an input pin of the digital-to-charge converter and to determine a difference between the target charge and the present charge. The DQC may further include a correction circuit coupled to the error determining circuit and configured to control a programmable current source to produce an analog signal at the output pin in response to the determined difference.