Digital Charge Pump PLL for Fast Lock and Fine Frequency Tuning
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Solution Overview
Problem
Phase lock loops (PLLs) require a shorter lock time to match the frequency and phase of a reference signal, particularly in applications like the Digital Mobil Radio standard, where locking within 1.5 ms for a 60 MHz frequency difference is necessary, but existing PLLs take longer to achieve lock.
Innovation Solution
A PLL design that includes a voltage-controlled oscillator (VCO), frequency detector, digital charge pump, loop filter, and state machine circuit, which iteratively reconfigures the digital charge pump to increase or decrease current to the loop filter based on FAST and SLOW signals, enabling faster locking by initially using high current levels and then transitioning to lower levels for precise adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional PLL uses fixed current levels in the charge pump, then the circuit is simple to implement, but the lock time is too long to meet stringent requirements
Solution Approach 1:
The charge pump current is made dynamic rather than fixed. The system transitions from a static current level to a dynamic current level that changes over time during the locking process. This is achieved through a state machine that controls the charge pump to provide high current initially for fast locking, then transitions to lower current for fine-tuning, thereby reducing lock time while managing complexity through structured control states.
Solution Approach 2:
The charge pump current parameter is changed over time based on the locking state. The system starts with a first current level for rapid frequency acquisition and then switches to a second, lower current level for precise phase and frequency adjustment. This parameter change approach allows the system to meet stringent lock time requirements by optimizing current levels for different stages of the locking process.
2Loss of time
If the PLL uses high current levels throughout the locking process, then the lock time is reduced, but the precision for fine-tuning frequency and phase is insufficient
Solution Approach 1:
The charge pump operates in periodic stages with different current levels. The system alternates between high-current periods for rapid locking and low-current periods for fine-tuning. This periodic action with varying current levels allows the PLL to achieve both fast lock time and high precision frequency/phase matching by optimizing the current level for each stage of the locking process.
Solution Approach 2:
The system performs preliminary high-current charging to quickly close the frequency gap, then transitions to low-current operation for precise adjustment. This preliminary action with high current gets the system close to the target frequency rapidly, and the subsequent low-current phase performs the fine-tuning needed for precise locking, thereby achieving both speed and accuracy.
3Loss of time
If the PLL transitions between different current levels, then the lock time is reduced, but the control logic complexity increases
Solution Approach 1:
The locking process is segmented into distinct phases, each handled by a specific state in the state machine. The system divides the complex task of frequency and phase locking into manageable segments: initial frequency acquisition with high current, transition phase, and fine-tuning with low current. This segmentation reduces control logic complexity by organizing the transitions into discrete, well-defined states and transitions.
Solution Approach 2:
The state machine uses feedback from the phase detector and frequency detector to determine when to transition between current levels. The system monitors the locking progress and automatically transitions from high-current mode to low-current mode when appropriate conditions are met. This feedback-based control reduces complexity by using simple threshold-based transition criteria rather than complex predictive algorithms.
Data Source
AI summary
A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase. Upon detection of a terminal condition, the state machine circuit may disable the digital charge pump and enable operation of an analog charge pump.