Digital CIM Accumulator Architecture for Accurate Edge Computation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computation-in-memory (CIM) processes using analog signals result in inaccuracy of neural network computations, and there is a need for more efficient and accurate processing of machine learning model data, particularly in edge devices with power and packaging constraints.
Innovation Solution
A digital CIM architecture utilizing digital counters and accumulators to perform in-memory computation, including a memory array with columns of memory cells storing neural network weights, digital counters coupled to each column, an adder circuit, and an accumulator to accumulate output signals, with self-timed operations and phase-shifting to reduce electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CIM processes use analog signals for computation, then computation can be performed in-memory, but computation accuracy deteriorates
Solution Approach 1:
The patent replaces analog signal-based computation with digital signal-based computation. Digital counters and accumulators process binary signals (0 and 1) instead of continuous analog voltages, eliminating the precision losses inherent in analog operations while maintaining in-memory computation capability through digital logic circuits integrated with memory arrays.
2Productivity
If dedicated hardware accelerators are used to process machine learning data, then processing capacity is enhanced, but space and power consumption increase
Solution Approach 1:
The patent merges memory storage and computation functions into a single integrated system. Weight data is stored directly in memory cells, and computation is performed by digital counters that process signals from these memory cells. This eliminates the need for separate dedicated hardware accelerators, reducing overall power consumption while maintaining high processing capacity for machine learning tasks.
Solution Approach 2:
The memory array serves multiple functions: it stores weight data, performs computation through digital counters, and accumulates results through shared accumulators. This multi-functional design eliminates the need for separate dedicated hardware components, reducing power consumption while maintaining enhanced processing capacity for machine learning workloads.
3Ease of operation
If data is moved across common data busses for processing, then data can be accessed by accelerators, but power usage increases and latency is introduced
Solution Approach 1:
The patent extracts the computation function from the data bus communication path. Instead of moving data through external data busses to accelerators, computation is performed directly within the memory array itself using integrated digital counters. This eliminates the energy-consuming and latency-prone data transfer process while maintaining ease of data access through the memory interface.
4Measurement precision
If digital counters and accumulators are used for in-memory computation, then computation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the computation function into multiple simple digital counters, each handling one column of memory cells independently. Each counter is a simple sequential circuit that increments on detecting a signal transition. This modular segmentation achieves accurate computation through multiple simple components rather than one complex system, improving accuracy while keeping individual component complexity low.
Solution Approach 2:
The patent uses a partial accumulation approach where only the necessary number of digital counters are deployed based on the memory array configuration. Each counter processes only its assigned column, and results are accumulated through shared accumulators. This partial action approach achieves sufficient computation accuracy without the excessive complexity of processing all possible data paths simultaneously.
Data Source
Figure 1A~1C
Figure 1D
Figure 2
AI summary
Certain aspects relate to performing machine learning tasks, and in particular, to computation-in-memory (CIM) architectures. One aspect provides a method for in-memory computation. The method generally includes: accumulating, via each digital counter of a plurality of digital counters, output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells storing multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; adding, via an adder circuit, output signals of the plurality of digital counters; and accumulating, via an accumulator, output signals of the adder circuit.