Digital Circuit Arc Reduction via Truth Table Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital circuit characterization techniques generate redundant timing arcs and fail to produce truth tables that include only valid arcs for each pin, leading to inefficient circuit representation and performance capture.
Innovation Solution
A method and system for digital circuit functionality recognition that involves receiving a truth table, determining valid arcs, forming a first arc table, identifying and removing redundant arcs to create a second arc table, and generating stimulus for each valid arc to characterize the circuit, thereby reducing redundant states and capturing essential circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional characterization tools generate timing arcs using full truth tables, then all possible states are captured, but redundant arcs are created that do not affect output transition
Solution Approach 1:
The patent extracts and removes redundant timing arcs from the full truth table by identifying arcs where secondary pin conditions do not affect the output transition. This is done by analyzing the truth table to determine which arcs are actually necessary for capturing circuit performance, thereby reducing the number of arcs while maintaining accuracy.
Solution Approach 2:
The patent changes the parameter representation by introducing state-dependent timing arcs with explicit state specifications. Instead of treating all arcs uniformly, it categorizes arcs based on their actual validity conditions, transforming the arc representation to include only necessary states and reducing overall complexity.
2Reliability
If all states are included for each timing arc, then complete circuit behavior is represented, but the liberty model size increases significantly
Solution Approach 1:
The patent extracts only the necessary states for each timing arc by analyzing which state combinations actually affect output transitions. States that do not influence the output are removed from the liberty model, significantly reducing model size while preserving complete circuit behavior representation.
3Manufacturing precision
If user explicitly specifies state dependent timing arcs, then precise control over arcs is achieved, but manual effort and time increase
Solution Approach 1:
The patent implements self-service by enabling the characterization tool to automatically identify and generate state-dependent timing arcs from the truth table without requiring explicit user specification. The system performs the analysis and arc generation autonomously, maintaining precision while eliminating manual effort and reducing characterization time.
4Productivity
If redundant arcs are removed to minimize the arc table, then efficiency improves, but risk of removing valid arcs increases
Solution Approach 1:
The patent implements feedback by systematically verifying each arc's validity through truth table analysis before removal. The method checks whether secondary pin conditions actually affect output transitions, providing a feedback mechanism that ensures only truly redundant arcs are removed, maintaining reliability while improving efficiency.
Data Source
AI summary
A method and system of digital circuit functionality recognition for circuit characterization is disclosed. In one embodiment, a method for determining the valid arcs includes receiving a truth table including state information associated with input pins and their associated output pins in the digital circuit. Valid arcs are then determined based on whether a change in each of the input pins causes a change in associated one of the output pins using the received truth table. A first arc table is then formed using state information associated with substantially the determined valid arcs. Redundant arcs are then identified in the first arc table using the associated state information. A second arc table is then formed by removing the state information associated with the redundant arcs from the first arc table.