Digital Circuit Error Simulation via Sub-Circuit Segmentation
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Solution Overview
Problem
Digital circuits face errors due to factors like alpha particles and low operating voltage, which can lead to fatal faults, and existing technologies lack effective simulation methods to determine error probabilities and verify fault-tolerant features in these systems.
Innovation Solution
An apparatus and method for error simulation that injects errors into a digital circuit, compares output data from a sub-circuit and a test circuit, and computes error probabilities using statistical processing, allowing for rapid determination of error rates and probabilities in full digital circuits through static analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full digital circuit simulation is performed using traditional RTL simulation methods, then error probability can be determined, but operating time becomes excessively long and complexity increases
Solution Approach 1:
The patent divides the full digital circuit into multiple sub-circuits and performs error simulation on each sub-circuit independently. The error probability of the entire circuit is then calculated by combining the error probabilities of individual sub-circuits using probability theory formulas. This segmentation approach dramatically reduces simulation time while maintaining accurate error probability determination for the complete circuit.
Solution Approach 2:
The patent extracts only the essential error simulation functionality from traditional RTL simulation, focusing specifically on error injection and detection mechanisms. By removing unnecessary simulation overhead and retaining only the critical error analysis components, the system achieves fast error probability calculation without the time penalty of full RTL simulation.
2Measurement precision
If full digital circuit simulation is performed using traditional RTL simulation methods, then error probability can be determined, but device complexity increases
Solution Approach 1:
The patent segments the complex full circuit simulation into simpler sub-circuit simulations. Each sub-circuit is simulated independently with reduced complexity, and the results are aggregated mathematically. This approach maintains measurement precision for error probability while significantly reducing the complexity of the simulation apparatus and methodology.
Solution Approach 2:
The patent creates simplified models of sub-circuits that capture only the essential error behavior characteristics needed for probability calculation. These simplified copies are used instead of full RTL representations, reducing simulation complexity while preserving the ability to accurately determine error probabilities through statistical analysis.
3Reliability
If error injection is performed on the entire digital circuit, then comprehensive error coverage is achieved, but simulation time and resource requirements increase significantly
Solution Approach 1:
The patent divides the error injection process into separate operations on individual sub-circuits. Each sub-circuit receives targeted error injection at its specific input nodes, and results are combined to achieve comprehensive error coverage for the entire circuit. This segmentation maintains thorough error coverage while improving simulation efficiency by avoiding the overhead of injecting errors into the complete circuit at once.
Data Source
AI summary
The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.