Digital Logic Circuit Fault Sensitivity Analysis and Remediation
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Solution Overview
Problem
Digital logic circuits are vulnerable to fault attacks, particularly Side Channel Attacks (SCA), which exploit fault sensitivity information, leading to potential exposure of secure data like cryptographic keys, and existing countermeasures do not effectively balance security with circuit size and overhead.
Innovation Solution
A system and method that assesses fault sensitivity using a metric called the fault sensitivity score, which accounts for signal arrival times and logic levels, and implements countermeasures such as inserting delay elements to balance delays and minimize overhead, using techniques like genetic algorithms to optimize the digital logic circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay elements are inserted to balance signal arrival times and reduce fault sensitivity, then security against fault attacks is improved, but circuit physical size and overhead increase
Solution Approach 1:
The patent changes the delay parameter of signal paths by inserting delay elements to equalize arrival times at logic gates. This parameter adjustment eliminates data-dependent timing variations that create fault sensitivity, thereby improving security without requiring fundamental circuit redesign
Solution Approach 2:
Delay elements are introduced as intermediary components between existing circuit elements. These intermediaries balance the timing of signals without altering the functional logic of the circuit, providing security hardening while maintaining original circuit behavior
2Measurement precision
If comprehensive fault sensitivity analysis is performed to identify all vulnerable points, then security assessment accuracy is improved, but analysis time and computational resources increase
Solution Approach 1:
The patent replaces traditional fault injection-based security assessment with a static timing analysis approach. This substitution eliminates the need for physical fault injections and iterative testing, providing comprehensive security assessment instantly through computational analysis of signal arrival times and logic gate dependencies
Data Source
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AI summary
The present specification is related to analysis of digital circuits for assessing a fault sensitivity of a digital logic circuit. An example method includes: obtaining a set of input vectors that represent possible inputs to the digital logic circuit; for each output gate of the plurality of digital logic gates: (i) for each input vector of the set of input vectors, determining a cumulative output delay for the output gate, and (ii) determining an averaged cumulative output delay for the output gate by averaging the cumulative output delays for the output gate that were determined for multiple input vectors of the set of input vectors; generating a fault sensitivity score for the digital logic circuit based on the averaged cumulative output delays for the output gates of the digital logic circuit; and providing the fault sensitivity score.