Digital Circuit Error Detection With Nonlinear Check Bits
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Solution Overview
Problem
Existing error detection codes in digital circuits, such as parity bit codes, Hamming codes, and Bose-Lin codes, are inefficient in detecting all errors, particularly failing to detect even errors and bidirectional 2-bit errors, which are common in high-integration electronic circuits due to radiation-induced soft errors.
Innovation Solution
A circuit arrangement is developed to generate check bits using nonlinear Boolean functions, allowing for the detection of all odd errors and a significant proportion of even errors with a minimal number of check bits, independent of the number of data bits, by combining information bits in specific subsets and using XOR and other logical operations to produce check bits that can detect errors with high probability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If parity bit code is used for error detection, then only a single additional check bit is required, but all errors that corrupt an even number of bits are not detected
Solution Approach 1:
The patent changes the parameter of check bit generation from linear XOR operations to nonlinear Boolean functions. Specifically, it uses functions like majority logic and weighted sums modulo 3, which fundamentally alter how check bits are computed to detect both odd and even number of errors while maintaining a constant number of check bits regardless of data size.
Solution Approach 2:
The patent applies different types of nonlinear Boolean functions to different subsets of data bits. For example, some check bits are generated using majority logic on specific bit groups, while others use weighted sums, creating local variations in error detection capability across different parts of the data stream.
2Reliability
If Hamming code is used to detect all 1-bit and 2-bit errors, then the number of check bits increases as the number of data bits increases, leading to high outlay
Solution Approach 1:
The patent creates a universal error detection code that works for any number of data bits using a fixed set of check bits. The nonlinear Boolean functions are designed to handle variable-length data streams without requiring the number of check bits to scale with data size, making the system universally applicable across different data widths.
Solution Approach 2:
The patent fundamentally changes the mathematical basis of error detection from linear algebra (Hamming code) to nonlinear Boolean logic. This parameter change allows the system to maintain constant check bit length while achieving comparable or superior error detection capability for both single and double bit errors.
3Reliability
If Berger code is used to detect unidirectional errors, then the number of check bits increases as the number of data bits increases, and bidirectional 2-bit errors cannot be detected
Solution Approach 1:
The patent combines multiple types of nonlinear Boolean functions (majority logic, weighted sums, XOR operations) into a composite error detection system. This composite approach leverages the strengths of each function type: majority logic for robust error detection, weighted sums for detecting bidirectional errors, and XOR for parity checking, achieving comprehensive error detection capability.
Solution Approach 2:
The patent changes the fundamental parameter of check bit generation from the simple count-based Berger code to nonlinear Boolean functions that consider the actual values and positions of data bits. This enables detection of bidirectional errors while maintaining a constant number of check bits independent of data length.
4Quantity of substance
If Reed-Solomon code is used for error correction, then the number of XOR elements can be reduced, but the circuit complexity and computational overhead increase
Solution Approach 1:
The patent uses simple, inexpensive nonlinear Boolean functions that can be implemented with minimal logic gates. These functions are computationally lightweight compared to Reed-Solomon decoding, achieving error detection with far fewer logical operations and simpler circuitry, effectively replacing complex error correction codes with simpler detection mechanisms.
Solution Approach 2:
The patent changes the computational approach from polynomial arithmetic over Galois fields (Reed-Solomon) to straightforward nonlinear Boolean logic operations. This parameter change dramatically reduces the number of logical operations required while maintaining effective error detection capability.
Data Source
AI summary
A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E1, . . . , En for inputting n (n≧2) information bits x1, . . . , xn and m binary outputs for outputting m (m≧1) check bits c1, . . . , cm. The combinational circuit is configured for realizing a Boolean function ci=fi(xi1, . . . , xini) for i=1, . . . , m at the i-th output for determining a check bit ci, wherein the set {xi1, . . . , xini} at the ni information bits that determine the check bit ci is a subset of all n information bits {x1, . . . , xn}. The combinational circuit is furthermore configured for realizing a first Boolean function f1(x11, . . . , x1n1) of the form c1=f1(x11, . . . , x1n1)=f11(x11, x12) XOR f12(x13, x14) XOR . . . XOR f1k1(x1(n1−1), x1n1) at a first output for outputting a first check bit c1, wherein n1 is an even number where n1≧2 and 2 k1=n1 and the Boolean functions f11(x11, x12), . . . , f1k1(x1(n1−1), x1n1) are in each case nonlinear Boolean functions of two variables which can be realized by logic gates having two inputs and one output, wherein the logic gates each have a controlling value c11, . . . , c1k1.