Digital Circuit Reverse Engineering Resistance via Threshold Voltage Asymmetry

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Solution Overview

Problem

Reverse engineering of integrated circuits poses a significant threat to the semiconductor industry, as attackers can steal and replicate circuit designs, and existing countermeasures are often costly and inefficient for mass production.

Innovation Solution

The method involves forming and connecting field effect transistors such that the output signal has an undefined logic state when threshold voltages are equal, and setting threshold voltages to achieve a predetermined defined logic state, using differently doped transistors to create metastable states that are shifted to stable states, thereby increasing the difficulty of reverse engineering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard field effect transistors with equal threshold voltages are used, then the circuit is easy to manufacture, but the output signal has an undefined logic state and the circuit is vulnerable to reverse engineering

Engineering Contradiction:
Improvesecurity against reverse engineeringVSAvoidthreshold voltage differentiation
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating asymmetric threshold voltage characteristics in specific transistor pairs within the circuit. While the overall circuit structure remains symmetric and manufacturable with standard processes, localized modifications to transistor threshold voltages (through doping variations or gate structure adjustments) create unique logical states that prevent reverse engineering. This allows the circuit to maintain general manufacturing simplicity while incorporating local security features.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs asymmetry by ensuring that at least one transistor in each pair has a different threshold voltage than its counterpart. This asymmetric threshold voltage configuration creates undefined or metastable logical states under specific input conditions, which serve as security features. The asymmetric design is implemented in a controlled manner that maintains overall circuit symmetry for manufacturability, creating a hierarchical structure where local asymmetry provides security while global symmetry enables standard production.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If threshold voltages are differentiated to create defined logic states, then reverse engineering difficulty increases, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedefined logic state stabilityVSAvoidthreshold voltage control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent utilizes parameter changes by systematically varying threshold voltage parameters across different transistor instances. Instead of requiring precise control of absolute threshold voltage values, the invention changes the relative threshold voltage parameters between paired transistors. This can be achieved through controlled doping concentration variations, different gate oxide thicknesses, or adjusted channel dimensions. The parameter changes are designed to create sufficient differentiation for security while remaining within standard manufacturing process capabilities.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9337156B2Method for manufacturing a digital circuit and digital circuit
Publication Date: 2016.05.10 INFINEON TECHNOLOGIES AG
  • US9337156B2 patent drawing
  • US9337156B2 patent drawing
  • US9337156B2 patent drawing

AI summary

A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input signal has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input signal has a predetermined defined logic state.