Digital Clock Divider for Integer and Half-Step Ratio Switching
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Solution Overview
Problem
Current clock dividers for high-speed System on Chip (SoC) designs face challenges in efficiently managing clock signals for integer, odd, and fractional divisions, particularly at frequencies above 600 MHz, with existing solutions either being non-scalable or requiring significant area overhead.
Innovation Solution
A high-speed clock divider capable of integer and half-step increments, ensuring 50% duty cycle and alignment of output clocks, with minimal logic gate count increase, allowing dynamic switching of divide ratios on the fly, suitable for operation at 1.0 GHz or higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing clock divider implementations are used for high-speed operations (>600 MHz), then clock division functionality is provided, but the designs either lack scalability or require significant area overhead
Solution Approach 1:
The clock divider is designed to perform multiple division operations (integer division by N, odd integer division, and N.5 division) using a unified architecture. The same core logic unit can be configured to execute different division algorithms by loading appropriate division factors, eliminating the need for separate dedicated circuits for each division type and reducing overall area overhead while maintaining high-speed operation
Solution Approach 2:
The clock divider implements dynamic reconfiguration capability where the division factor can be changed on-the-fly without requiring physical circuit reconfiguration. This is achieved through programmable control logic that loads different division factors into register files, allowing the same hardware to adapt to different division requirements dynamically while maintaining high-speed performance
2Speed
If existing clock divider implementations are used for high-speed operations (>600 MHz), then clock division functionality is provided, but the designs lack scalability
Solution Approach 1:
The clock divider architecture is designed to support multiple division modes (integer, odd integer, and fractional) within a single unified structure. By using programmable control logic and configurable register files, the same hardware can be scaled to support different division factors and modes without requiring fundamental architectural changes, enabling both high-speed operation and scalability
Solution Approach 2:
The clock divider enables scalability through parameter reconfiguration rather than structural modification. Division factors, clock select signals, and control parameters can be dynamically adjusted to change the division behavior, allowing the same hardware to scale from simple integer division to complex fractional division operations while maintaining high-speed performance
3Adaptability or versatility
If dynamic switching of divide ratios is implemented, then optimal peripheral operation is enabled, but logic gate count increases
Solution Approach 1:
The clock divider implements dynamic divide ratio switching through programmable control logic that loads division factors from register files. This dynamic reconfiguration is achieved by changing control parameters rather than physically reconfiguring the logic structure, enabling optimal peripheral operation while keeping the increase in logic gate count minimal compared to static implementations
Solution Approach 2:
The clock divider uses pre-loaded register files that store division factors and control parameters. By preparing these parameters in advance and loading them into registers, the system enables rapid dynamic switching of divide ratios without requiring complex real-time calculation logic, thus reducing the overall logic gate count while maintaining adaptability
Data Source
AI summary
A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.