Digital Output Clock Scaling With Drift Compensation
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Solution Overview
Problem
Existing clock generation solutions for display outputs, such as those using analog Phase Locked Loop (PLL) circuits, consume significant die area and power, lack flexibility, and do not scale well with the number of display sources, while simple dividers fail to provide adequate frequency scaling and drift compensation.
Innovation Solution
A highly portable, area-efficient design using digital logic and integer arithmetic to approximate a variable frequency oscillator, providing scalable digital waveforms with programmable drift compensation, which eliminates the need for costly analog components like PLLs and allows for flexible frequency scaling without the need for hardware multipliers or dividers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog Phase Locked Loop (PLL) circuits are used for clock generation, then clock accuracy and stability are improved, but die area consumption and power usage increase significantly
Solution Approach 1:
The patent replaces analog PLL circuits with a digital clock generation system using integer arithmetic and line drawing techniques. This substitution eliminates the need for complex analog components while maintaining clock accuracy through digital computation of clock edges based on accumulated error correction.
Solution Approach 2:
The patent changes the operational parameters from continuous analog domain to discrete digital domain. By using integer ratios and digital accumulation methods, the system achieves comparable clock accuracy without the physical constraints and area requirements of analog PLL circuits.
2Stability of the object's composition
If analog Phase Locked Loop (PLL) circuits are used for clock generation, then clock stability is improved, but power consumption increases
Solution Approach 1:
The patent substitutes power-hungry analog PLL circuits with low-power digital logic implementations. The digital arithmetic operations and lookup table methods consume significantly less power while maintaining clock stability through algorithmic error compensation.
3Device complexity
If simple dividers are used for frequency scaling, then device complexity is reduced, but frequency scaling range and drift compensation capability are insufficient
Solution Approach 1:
The patent introduces dynamic frequency scaling capability through programmable integer ratios and accumulators that can adapt to different frequency requirements. The system dynamically adjusts clock generation parameters based on desired output frequency while maintaining simplicity through algorithmic control.
Solution Approach 2:
The patent creates a universal clock generation platform that can serve multiple frequency scaling needs through a single implementation. The integer arithmetic and line drawing technique provide a multi-functional solution that handles various frequency ratios and drift compensation scenarios without requiring separate dedicated circuits.
4Reliability
If multiple analog PLL circuits are replicated for multiple display sources, then each source receives accurate clock, but die area and resource consumption scale poorly
Solution Approach 1:
The patent implements a universal digital clock generation engine that can service multiple display sources simultaneously. The same integer arithmetic and accumulation logic can be configured for different frequency requirements, eliminating the need to replicate entire PLL circuits for each display source.
Solution Approach 2:
The patent segments the clock generation function into independent configurable units that can be shared across multiple display sources. Each display source receives appropriately scaled clock signals through digital division and accumulation rather than requiring dedicated analog PLL instances.
Data Source
AI summary
An example device in accordance with an aspect of the present disclosure includes a first stage and an accumulator. The first stage is based on digital logic and integer arithmetic to scale a reference clock by a configurable ratio of integers according to a line drawing technique to obtain an output clock. The accumulator is to store an accumulated error of a variable used in the line drawing technique.