Full-Digital Clock Duty-Cycle Correction Without TDC Area Penalty
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Solution Overview
Problem
Existing digital duty cycle correction circuits face challenges in maintaining accurate duty cycle correction across a wide frequency range and large duty cycle variations, leading to increased circuit area and error rates due to the limitations of time-to-digital converter (TDC) architecture.
Innovation Solution
A full-digital clock duty cycle correction circuit comprising a sampling unit, a duty cycle correcting module, and a phase-lock module that adjusts pulse widths and aligns positive edges of clock signals to achieve precise 50% duty cycle correction, reducing chip area and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If TDC architecture is used for duty cycle correction, then wide frequency range support is achieved, but circuit area increases significantly
Solution Approach 1:
The patent extracts and removes the TDC architecture from the duty cycle correction circuit. By eliminating the TDC block entirely, the circuit area is significantly reduced while maintaining wide frequency range support through alternative delay element design and phase comparison mechanisms that do not require TDC quantization.
Solution Approach 2:
The patent segments the duty cycle correction function into separate delay elements with adjustable delay times. Instead of using a monolithic TDC architecture, the correction is divided into multiple adjustable delay stages that can be independently tuned, reducing overall circuit complexity and area while maintaining adaptability across frequency ranges.
2Adaptability or versatility
If TDC architecture is used for duty cycle correction, then frequency range coverage is improved, but duty cycle correction accuracy deteriorates
Solution Approach 1:
The patent implements dynamic adjustment of delay element parameters based on the input clock frequency. The delay times of the delay elements are made可调 (adjustable) to dynamically adapt to different frequency ranges, ensuring that the phase comparison remains accurate across the entire frequency spectrum without requiring fixed TDC quantization levels.
Solution Approach 2:
The patent changes the delay time parameters of the delay elements according to the operating frequency. By adjusting the delay parameters dynamically, the system maintains high duty cycle correction accuracy across wide frequency ranges, avoiding the accuracy degradation inherent in fixed-resolution TDC architectures.
3Adaptability or versatility
If TDC architecture is used, then half-cycle delay circuit is required, but tuning accuracy becomes limited to twice TDC accuracy
Solution Approach 1:
The patent inverts the traditional approach by eliminating the half-cycle delay circuit requirement. Instead of using TDC to quantize and then generating half-cycle delay, the system directly compares phases of complementary clock signals and adjusts delay elements to achieve 50% duty cycle without requiring the intermediate half-cycle delay stage, thereby achieving tuning accuracy equal to TDC accuracy rather than twice that value.
4Manufacturing precision
If duty cycle correction is implemented, then 50% duty cycle is achieved, but chip area increases
Solution Approach 1:
The patent merges the duty cycle correction function with the existing clock distribution network by using complementary clock signals (CLK and /CLK) that are already present in the system. The delay elements are integrated into the existing clock paths, and the phase comparison is performed using signals already available, eliminating the need for separate correction circuitry and reducing overall chip area.
Solution Approach 2:
The system uses the existing complementary clock signals and their inherent phase relationship to perform self-correction. The delay elements automatically adjust the phase of one clock signal relative to its complement, and the phase comparison mechanism uses the existing signal relationships, allowing the system to correct its own duty cycle without requiring extensive external correction circuitry.
Data Source
AI summary
The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.