Digital Clock Recovery Circuit for Fast Locking Without Reference Clock
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Solution Overview
Problem
Existing clock data recovery circuits face challenges in reducing locking time while efficiently configuring the size and configuration, particularly in high-speed data transmission scenarios.
Innovation Solution
A digital clock data recovery device that operates without a reference clock, utilizing a phase difference compensation unit, digital loop filter, and digital controlled oscillator to recover clock and data, with a scalable and reduced circuit size, and includes a Time-to-Digital Converter (TDC) and phase detector for fast locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional clock data recovery circuit is used, then the circuit can recover clock and data from serial data, but the locking time is prolonged and the circuit size increases
Solution Approach 1:
The phase difference compensation unit is divided into multiple sub-units: a coarse compensation unit that handles large phase differences and a fine compensation unit that handles small phase differences. This segmentation allows the circuit to quickly acquire lock (coarse) and then precisely maintain lock (fine), reducing overall locking time without requiring a large circuit for all compensation ranges.
Solution Approach 2:
The circuit dynamically switches between different compensation modes based on the current phase difference magnitude. When the phase difference exceeds a threshold, the coarse compensation unit is activated; when it falls within the threshold, the fine compensation unit takes over. This dynamic adaptation optimizes both locking speed and circuit efficiency.
2Device complexity
If the circuit size is reduced, then the locking time may increase, but the patent achieves both reduced size and fast locking
Solution Approach 1:
By segmenting the compensation range into coarse and fine portions, the circuit avoids the need for a single large compensation unit that would cover the entire phase difference range. Each sub-unit is smaller and more efficient, collectively providing comprehensive compensation while maintaining compact size.
Solution Approach 2:
The patent replaces traditional analog phase-locked loop mechanisms with a fully digital implementation. The digital phase difference compensation unit uses digital logic and algorithms to achieve phase alignment, which reduces hardware complexity and circuit size while maintaining or improving locking performance through programmable control.
3Adaptability or versatility
If a fully digital circuit is implemented, then scalability across protocols is improved and circuit size is reduced, but operating without a reference clock increases difficulty
Solution Approach 1:
The circuit extracts the embedded clock signal directly from the incoming serial data itself, without requiring an external reference clock. The phase difference compensation unit uses the data transitions to generate and synchronize the embedded clock, making the system self-sufficient and adaptable to different protocols that use embedded clocking schemes.
Solution Approach 2:
The digital phase difference compensation unit is designed with programmable parameters and configurable compensation ranges that can be adjusted to match different protocol requirements. This universal design allows the same circuit architecture to work across multiple serial communication protocols that use embedded clocking, enhancing scalability and versatility.
Data Source
AI summary
A digital clock data recovery device for recovering a clock and data in a data signal includes a phase difference compensation unit configured to selectively output an upper bit value and a lower bit value of a phase difference value between a first input signal and a second input signal according to a condition based on a range of the phase difference value, a digital loop filter configured to receive an output of the phase difference compensation unit; and a digital controlled oscillator configured to transfer a feedback signal to the phase difference compensation unit based on an output value of the digital loop filter.