Digital Clock Delay Line With Feedback for Duty Cycle Control
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Solution Overview
Problem
Modern integrated circuits face challenges in generating high-frequency clock signals with predictable duty cycles due to process, voltage, and temperature variations, as existing phase lock loop (PLL) circuitry is area and power hungry, and analog or RF designs are complicated by these variations.
Innovation Solution
A digital circuit design using a series of identical delay units in a delay line with feedback circuitry to generate multiple delayed versions of an input clock, allowing for selection of a desired delayed clock and adjustment of the number of delay units to compensate for variations, thereby producing clocks with controlled duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase lock loop (PLL) circuitry is used to generate high-frequency clock signals, then the clock generation is reliable and stable, but the circuit area increases and power consumption increases
Solution Approach 1:
The clock generation function is segmented into multiple identical delay units (first delay units 202_1 through 202_n) arranged in series, each contributing a portion of the total delay. This segmentation replaces the monolithic PLL structure with modular delay elements, reducing overall circuit area while maintaining clock generation stability through the cumulative delay effect.
Solution Approach 2:
The delay line circuitry serves multiple functions: it generates delayed versions of the clock signal for frequency multiplication, provides feedback for duty cycle correction, and enables selection of different delay amounts through the clock selection signal. This multi-functionality eliminates the need for separate PLL components, reducing circuit area while maintaining reliability.
2Reliability
If phase lock loop (PLL) circuitry is used to generate high-frequency clock signals, then the clock generation is reliable and stable, but the power consumption increases
Solution Approach 1:
The power consumption is segmented and distributed across multiple simple delay units rather than concentrated in a power-hungry PLL. Each delay unit consumes minimal power, and the cumulative effect achieves the desired clock generation stability, thereby reducing total power consumption while maintaining reliability.
Solution Approach 2:
Instead of using a complex PLL that consumes high power, the invention creates multiple copies of simple delay units that replicate the timing function. These copied delay elements consume far less power individually and collectively, while still achieving reliable clock generation through their combined delay effect.
3Ease of manufacture
If a delay line is used to generate high-frequency clock signals with a digital design, then the circuit is easier to design and less power hungry, but the duty cycle becomes uncertain and unpredictable due to process, voltage, and temperature variations
Solution Approach 1:
A feedback path is introduced where a delayed version of the clock signal is fed back through XOR gates to the delay line inputs. This feedback mechanism automatically adjusts the delay amount to compensate for process, voltage, and temperature variations, thereby maintaining accurate duty cycle while preserving the simplicity of the digital delay line design.
Solution Approach 2:
The invention dynamically changes the delay parameter of the delay line based on feedback from the clock signal characteristics. By adjusting the delay amount in response to PVT variations, the system maintains precise duty cycle control while keeping the overall design simple and digitally implementable.
4Measurement precision
If the number of delay units is increased to achieve desired delay, then the delay precision improves, but the circuit area and complexity increase
Solution Approach 1:
The delay line is made dynamic and adjustable through the clock selection signal, which selectively enables or disables individual delay units based on the desired delay amount and PVT conditions. This dynamic configuration allows precise delay control with fewer physical delay units, reducing circuit area while maintaining delay precision through adaptive selection.
Data Source
AI summary
In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.