Digital Clock Frequency Detection for Non-50% Duty Cycles
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Solution Overview
Problem
Conventional frequency detecting circuits for semiconductor apparatuses, such as smart cards, face challenges in accurately detecting frequencies with non-50% duty cycle clock signals, leading to potential operational errors and high power consumption due to their analog RC filter implementation.
Innovation Solution
A digital frequency detecting circuit comprising an edge detecting circuit, a clock signal generating circuit, and a determination circuit that detects the frequency by analyzing the number of occurrences of a selection clock signal during each period of the clock signal, allowing for accurate detection even with non-standard duty cycles and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog RC filter is used for frequency detection, then the circuit can detect frequency, but a large chip area is needed and a large amount of power is consumed
Solution Approach 1:
The patent replaces the analog RC filter (electrical/mechanical system) with a digital frequency detection circuit that uses digital logic components such as flip-flops, counters, and logic gates. This substitution converts the analog frequency detection method into a digital one, thereby reducing chip area and power consumption while maintaining frequency detection capability.
Solution Approach 2:
The patent changes the operating parameters by using digital logic levels and discrete digital components instead of continuous analog signals and RC time constants. The frequency detection is achieved through digital counting and comparison of clock cycles, fundamentally changing the parameter space from analog to digital domain.
2Measurement precision
If an analog RC filter is used for frequency detection, then the circuit can detect frequency, but a large amount of power is consumed
Solution Approach 1:
The patent replaces the analog RC filter (electrical/mechanical system) with a digital frequency detection circuit that uses digital logic components such as flip-flops, counters, and logic gates. This substitution converts the analog frequency detection method into a digital one, thereby reducing chip area and power consumption while maintaining frequency detection capability.
Solution Approach 2:
The digital frequency detection circuit operates by sampling the clock signal at specific periodic intervals using flip-flops triggered on rising or falling edges. This periodic sampling approach allows accurate frequency measurement while consuming power only during active sampling periods, rather than continuously as in analog RC filters.
3Measurement precision
If the clock signal does not have a duty cycle of 50%, then the frequency cannot be detected using the analog method, but the semiconductor device may operate erroneously
Solution Approach 1:
The patent employs dynamic triggering mechanisms where the detection circuit can be configured to respond to either rising edges or falling edges of the clock signal. This dynamic adaptability allows the circuit to accurately detect frequency regardless of the duty cycle, as it can select the appropriate edge type based on the signal characteristics, thereby maintaining both detection accuracy and operational reliability.
Solution Approach 2:
The patent changes the operating parameters by using digital logic levels and discrete digital components instead of continuous analog signals and RC time constants. The frequency detection is achieved through digital counting and comparison of clock cycles, fundamentally changing the parameter space from analog to digital domain.
4Productivity
If conventional frequency detection methods are used, then the circuit operates, but accuracy and reliability are reduced when duty cycle is not 50%
Solution Approach 1:
The patent employs dynamic triggering mechanisms where the detection circuit can be configured to respond to either rising edges or falling edges of the clock signal. This dynamic adaptability allows the circuit to accurately detect frequency regardless of the duty cycle, as it can select the appropriate edge type based on the signal characteristics, thereby maintaining both detection accuracy and operational reliability.
Solution Approach 2:
The digital frequency detection circuit is designed to handle multiple scenarios universally - it can detect frequencies for clock signals with any duty cycle (50% or non-50%), making it a universal solution that covers all operational cases where conventional analog methods fail.
Data Source
AI summary
A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge detecting circuit detects an edge of an input clock signal. The clock signal generating circuit generates a selection clock signal, which is a periodic pulse signal, in response to the detected edge. The determination circuit generates a frequency detection signal based on the number of occurrences of the selection clock signal in a period of the clock signal. The semiconductor apparatus includes the above-described frequency detecting circuit and a processor resetting the semiconductor apparatus in response to the frequency detection signal. Since a frequency is detected every half period, that is every high/low level period, of the clock signal in a digital manner, the reliability and the accuracy of frequency detection is improved.