Digital Clock Circuit With Frequency-Locked High-Ratio Multiplication
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Solution Overview
Problem
Conventional clock circuits with phase locked loop (PLL) designs face limitations in achieving ultra-large frequency multiplier/divider factors due to increased jitter in the output clock signal, which degrades signal quality and restricts the integration of high-frequency clock signals in chips.
Innovation Solution
A digital clock circuit utilizing a free-running oscillation-based approach to generate high-ratio frequency multiplication clock signals, incorporating a first digitally-controlled oscillator and a time-average-frequency frequency-locked loop to control the frequency multiplication process without relying on crystal oscillators or voltage pulse sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency multiplier/divider factor is increased in conventional PLL designs, then the output clock frequency is improved, but the jitter in the output becomes larger and signal quality degrades
Solution Approach 1:
The patent segments the frequency multiplication process into multiple stages using a cascaded counter structure. Instead of achieving ultra-large frequency multiplication (e.g., 1000x) in a single PLL stage, the system divides the multiplication into several smaller steps, each handled by individual counter stages. This segmentation prevents the jitter accumulation that occurs in single-stage high-ratio multiplication while achieving the desired overall frequency multiplication effect.
Solution Approach 2:
The patent employs dynamic frequency multiplication where the multiplication ratio is not fixed but can be adjusted in real-time. The system uses a programmable counter that can dynamically change its division ratio based on control signals, allowing the PLL to adaptively optimize the frequency multiplication path. This dynamic approach enables the system to select optimal intermediate multiplication stages that minimize jitter while achieving the target frequency.
2Speed
If the frequency multiplier factor is set to ultra-large values (e.g., 1000x), then high-frequency clock signals can be generated, but conventional PLL designs cannot maintain acceptable jitter levels
Solution Approach 1:
The patent implements segmentation by dividing the ultra-large frequency multiplication into multiple manageable stages. The cascaded counter structure allows each stage to handle a moderate multiplication factor (e.g., 10x per stage), and the combined effect of multiple stages achieves the overall ultra-large multiplication (e.g., 1000x). This approach maintains jitter within acceptable limits at each stage while achieving the target high-frequency output.
Solution Approach 2:
The patent utilizes feedback mechanisms through the PLL architecture to continuously monitor and adjust the frequency multiplication process. The phase detector compares the divided feedback signal with the reference signal, and the resulting error signal adjusts the VCO frequency to maintain precise frequency multiplication. This feedback control ensures that even with ultra-large multiplication ratios, the output frequency and phase remain accurately locked to the reference, minimizing jitter.
Data Source
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AI summary
A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multiple first pulses, and a first frequency divider to generate a trigger signal having a frequency equal to 1/M of the first output frequency. The digital clock circuit also includes a second sub-circuit comprising a loop of feedback including a frequency detector to compare an input frequency with a feedback frequency, a controller to adjust the frequency control word, a second digitally-controlled oscillator driven by the frequency control word plus a constant to control a second output frequency synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider to set the feedback frequency equal to 1/N of the second output frequency in the loop of feedback.