Digital Clock Recovery Circuit for High-Speed Jitter Control
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Solution Overview
Problem
Conventional clock and data recovery circuits face challenges in high-speed operations due to deteriorated jitter characteristics and complexity, particularly with the mixture of digital and analog circuits, leading to increased chip area and difficulty in recovering clock signals and data.
Innovation Solution
A clock and data recovery circuit utilizing time-to-digital conversion circuits to compare the phase differences between input and recovery clock signals, enabling the generation of recovery clock signals and data, with a digital loop filter and digitally controlled oscillator to simplify the configuration and facilitate high-speed data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock and data recovery circuit with bang-bang phase detector is used, then the circuit can recover clock signal and data, but the jitter characteristic deteriorates in high-speed operation
Solution Approach 1:
The patent replaces the analog bang-bang phase detector with a digital time-to-digital conversion circuit. This substitution transforms the phase detection mechanism from an analog system to a digital system, enabling accurate phase measurement even at high data transmission speeds where analog circuits suffer from jitter degradation. The digital TDC circuit converts time differences into digital values that can be processed without the jitter issues inherent in analog high-speed operation.
Solution Approach 2:
The patent changes the operational parameters by using multiple clock signals with different phases (first clock signal, second clock signal, third clock signal) instead of a single clock signal. This parameter change allows the circuit to sample and detect phase differences at multiple time points, improving the accuracy of phase detection and reducing jitter effects in high-speed operation.
2Reliability
If a common clock and data recovery circuit with mixture of digital and analog circuits is used, then the circuit can recover clock signal and data, but the circuit complexity increases
Solution Approach 1:
The patent replaces the mixed digital-analog circuit architecture with a fully digital circuit implementation. The time-to-digital conversion circuit, digital loop filter, and digitally controlled oscillator work entirely in the digital domain, eliminating the need for analog components and reducing overall circuit complexity while maintaining reliable clock and data recovery functionality.
Solution Approach 2:
The patent creates a universal digital circuit architecture that can handle both clock recovery and data recovery functions within a unified digital framework. The same digital TDC circuit, digital loop filter, and digitally controlled oscillator work together to perform multiple functions (phase detection, phase adjustment, data sampling) without requiring separate analog circuits for each function.
3Reliability
If a common clock and data recovery circuit with passive element is used, then the circuit can recover clock signal and data, but the chip area increases
Solution Approach 1:
The patent replaces passive elements (such as resistors, capacitors, and inductors) with digital circuit components. The time-to-digital conversion is achieved through digital logic circuits and timing mechanisms rather than passive RC time constants or LC resonators, significantly reducing the chip area required while maintaining the clock and data recovery function.
4Device complexity
If time-to-digital conversion circuit is used to compare phase differences, then the circuit configuration is simplified and high-speed recovery is enabled, but the circuit requires multiple clock signals with different phases
Solution Approach 1:
The patent uses a digitally controlled oscillator that can dynamically adjust the phases of multiple clock signals based on digital control inputs. This dynamic capability allows the circuit to generate the required multiple phased clock signals on-demand, transforming a static circuit into an adaptive system that can provide the necessary clock signals with different phases as needed for the time-to-digital conversion process.
Solution Approach 2:
The patent implements a feedback loop where the digital loop filter processes the digital phase difference information and generates control signals that feed back to the digitally controlled oscillator. This feedback mechanism automatically adjusts the clock signal phases to achieve the desired phase relationships, simplifying the overall circuit configuration by using control theory to manage the multiple clock signal requirements.
Data Source
AI summary
The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.