Digital Clock Synchronization for Jitter-Suppressed Data Links
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Solution Overview
Problem
High-speed data transmission interfaces suffer from signal attenuation and intersymbol interference, leading to jitter in receiver signals, which requires large loop filters to suppress, increasing overall costs.
Innovation Solution
A clock control device comprising a phase interpolator circuit, detector circuit, and digital controller circuitry that generates a second reference clock signal and error signal to synchronize the transmitter clock signal with the receiver signal, reducing jitter without the need for a large loop filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a re-timer is utilized to retime a signal, then the receiver end can receive correct signals, but the output signal may have jitter(s)
Solution Approach 1:
The patent implements a feedback mechanism where the receiver detects jitter in the received signal and sends control information back to the transmitter. The transmitter uses this feedback to adjust its clock signal phase, thereby suppressing jitter at the source rather than merely retiming the signal at the receiver end.
Solution Approach 2:
The patent introduces a clock control device as an intermediary between the transmitter and receiver. This device includes a phase interpolator that generates adjusted clock signals based on feedback control, acting as a mediator to synchronize clocks and reduce jitter without requiring large loop filters at the receiver end.
2Object-generated harmful factors
If a loop filter having larger area is employed for filtering operation, then jitter(s) can be suppressed, but overall costs increase significantly
Solution Approach 1:
The patent replaces the traditional analog loop filter with a digital control system. Instead of using a large-area analog loop filter for jitter suppression, the system uses digital signal processing with a phase interpolator and digital controller that can achieve jitter reduction with significantly reduced hardware area and complexity.
Solution Approach 2:
The patent changes the operating parameters by using digital control signals to adjust the phase interpolator's output. By varying digital control words rather than analog filter parameters, the system achieves flexible jitter suppression with compact implementation, avoiding the need for large-area analog components.
Data Source
AI summary
A clock device includes a first phase interpolator circuit, a detector circuit, and a digital controller circuitry. The first phase interpolator circuit generates a second reference clock signal according to a first control signal and at least one first reference clock signal. The detector circuit generates an error signal according to a difference between a receiver signal and the second reference clock signal, in which the receiver signal is a receiver clock signal from a receiver circuit or an input signal that has been equalized by the receiver circuit. The digital controller circuitry generates the first control signal and a second control signal according to the error signal, and updates the second control signal according to a change of the first control signal, in which the second control signal is for generating a transmitter clock signal of a transmitter circuit.