Digital Clock Synchronizer for Low-Jitter Multi-Channel Timing
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Solution Overview
Problem
Existing clock synchronizers face challenges in minimizing jitter in local clocks due to frequency errors and interference, leading to data loss and distortion, especially in multi-channel systems, where large off-chip components are required to filter out jitter, increasing cost and physical size while potentially introducing more jitter.
Innovation Solution
A clock synchronizer system using a phase-locked-loop circuit with a controllable divider and a clock comparison circuit to adjust the frequency division value, reducing asynchronism between local and received clocks, thereby generating a low-jitter local clock signal synchronized with the received clock, utilizing digital means to achieve low loop bandwidth and minimize jitter transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large off-chip components are used to filter out jitter in traditional analogue phase locked loops, then jitter attenuation is improved, but device complexity and physical size increase
Solution Approach 1:
The patent replaces the mechanical/analog filtering system (large off-chip components in traditional analogue PLLs) with a digital control system. The digital frequency-locked loop uses digital signal processing to achieve jitter attenuation without requiring large physical filtering components, thus reducing device complexity while maintaining reliability.
Solution Approach 2:
The invention changes the operating parameters by using a digital control approach that can dynamically adjust the loop bandwidth and filtering characteristics through software or digital logic rather than fixed analog components. This allows flexible optimization of jitter attenuation performance without increasing physical hardware size.
2Reliability
If a separate clock channel is used to transmit clock signals, then clock synchronization is improved, but susceptibility to noise and interference increases
Solution Approach 1:
The patent merges the clock signal transmission with the data signal transmission by extracting the clock information from the data stream itself. This eliminates the need for a separate clock channel that would be susceptible to noise and interference, while maintaining accurate clock synchronization through digital recovery techniques.
Solution Approach 2:
The invention uses the data signal as an intermediary carrier for clock information. Instead of transmitting a separate clock signal that could be corrupted by noise, the system embeds clock information within the data stream and uses digital signal processing to extract and recover the clock signal, thereby protecting it from external interference.
3Reliability
If elastic buffer size is increased to prevent data loss in multi-channel systems, then data loss prevention is improved, but memory requirements and system complexity increase
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors clock synchronization status and dynamically adjusts buffer management parameters. The frequency-locked loop provides real-time feedback on clock drift, allowing the system to optimize buffer size dynamically rather than allocating excessive static memory, thus preventing data loss while minimizing memory requirements.
Solution Approach 2:
The invention introduces dynamic buffer management that adapts to changing system conditions. Instead of using fixed large buffers for all channels, the system dynamically adjusts buffer allocation based on real-time clock synchronization status and data flow characteristics, preventing data loss only when necessary while reducing overall memory requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively reduces jitter in the local clock, ensuring synchronization with the received clock, improving signal quality and reducing hardware requirements, particularly in multi-channel systems, by decoupling high-frequency jitter components and allowing for a common clock synchronization across all channels.
Implementation Method 1
a phase-locked-loop circuit including a phase detector, having a first input arranged to receive the reference signal
Implementation Method 2
a controllable divider arranged in a feedback path from a controlled oscillator to a second input of the phase detector, the divider being controllable to set a frequency division value N
Implementation Method 3
a controlled oscillator to provide a local clock signal at a frequency which is a multiple of the reference frequency
Implementation Method 4
a clock comparison circuit arranged to receive the local clock signal and a received clock signal, and adapted to generate a first digital signal indicative of an asynchronism between the local and received clock signals
Data Source
AI summary
A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. Preferably, the clock comparison circuit compares the periods of the local and received clock signals.