Digital Multiphase Clock Interpolation for Low Skew and Jitter
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Solution Overview
Problem
Data centers face challenges in power consumption, jitter, and skew that impact Signal-to-Noise and Distortion Ratio (SNDR) due to increasing bandwidth demands, with existing multiphase clock generators being area and power inefficient, particularly in analog phase interpolators, and requiring large DACs for control.
Innovation Solution
A multiphase clock generator using digital phase interpolators with a binary to thermometer decoder and control code latches, employing a calibration method that takes advantage of inherent non-linearity to reduce skew and area, and a cascaded coarse and fine deskew stage to minimize power and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog phase interpolators are used in multiphase clock generators, then phase interpolation function is achieved, but area and power consumption increase significantly
Solution Approach 1:
The patent replaces analog phase interpolators with digital phase interpolators, substituting continuous analog circuitry with discrete digital logic elements. This substitution dramatically reduces area consumption while maintaining the phase interpolation function through binary-to-thermometer decoding and digital signal processing techniques.
2Adaptability or versatility
If analog phase interpolators are used in multiphase clock generators, then phase interpolation function is achieved, but power consumption increases significantly
Solution Approach 1:
The patent replaces analog phase interpolators with digital phase interpolators, substituting continuous analog circuitry with discrete digital logic elements. This substitution dramatically reduces power consumption while maintaining the phase interpolation function through binary-to-thermometer decoding and digital signal processing techniques.
3Measurement precision
If large DACs are used for control in multiphase clock generators, then control precision is improved, but area consumption increases
Solution Approach 1:
The patent segments the control function by using binary-to-thermometer decoders that convert compact binary control codes into thermometer-coded signals. This segmentation allows high control precision to be achieved with minimal DAC size, as the binary representation requires far fewer bits than direct thermometer coding, thereby reducing area consumption while maintaining precision.
4Productivity
If clocking speed is increased to meet bandwidth demands, then data transmission rate is improved, but jitter and skew increase impacting SNDR
Solution Approach 1:
The patent employs deskew stages that monitor and correct clock phase alignment in real-time. By implementing feedback mechanisms that detect and compensate for skew and jitter, the system maintains high SNDR even at increased clocking speeds, allowing improved data transmission rates without sacrificing reliability.
Data Source
AI summary
Aspects of the subject disclosure may include, for example, a multiphase clock generator having a plurality of digital phase interpolators each configured to create a generated clock signal according to an applied digital code, wherein a first digital code applied to a first digital phase interpolator and a second digital code applied to a second digital phase interpolator are chosen in a less precise range such that a first generated clock signal output by the first digital phase interpolator is as close to an ideal phase separation from a second generated clock signal output by the second digital phase interpolator, and wherein additional codes are applied to other digital phase interpolators in a more precise range to create generated clock signals having a deviation from an ideal separation from the first generated clock signal or the second generated clock signal that is less than a linear resolution of the applied digital code. Other embodiments are disclosed.