All-Digital Clock Generator for Fast Multi-Rate Frequency Switching
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Solution Overview
Problem
Existing clock generator technologies are complex and inflexible, particularly in multi-rate clock domain designs, due to reliance on digitally-controlled oscillators or voltage controlled oscillators, which are costly and difficult to adjust quickly.
Innovation Solution
An all-digital clock generator system comprising a digitally-controlled clock generator, a time-to-digital converter, and a processing unit, which uses a frequency multiplier and delay control units to generate clock signals with adjustable frequencies and supports multi-rate clock domains through a semi-synchronous architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digitally-controlled oscillators or voltage controlled oscillators are used for frequency adjustment, then frequency adjustment capability is achieved, but hardware complexity and cost increase
Solution Approach 1:
The patent replaces the traditional voltage-controlled oscillator (VCO) or digitally-controlled oscillator (DCO) with a fully digital frequency synthesis approach using integer-N PLL architecture. The frequency adjustment is achieved through digital division ratios in the feedback path rather than analog voltage control, eliminating the need for complex analog oscillation control circuits while maintaining frequency adjustment capability.
Solution Approach 2:
The patent uses a reference clock signal as a template and generates multiple output clock signals by digitally dividing or multiplying this reference. The frequency synthesis is accomplished by copying the reference signal and applying digital frequency multiplication/division, avoiding the need for separate VCO circuits for each frequency output.
2Reliability
If traditional phase-locked loop architecture is used, then frequency stability is maintained, but frequency adjustment speed is slow
Solution Approach 1:
The patent replaces the analog frequency tuning mechanism in traditional PLLs with a fully digital frequency synthesis approach. The integer-N PLL uses digital counters and dividers to achieve frequency multiplication and division, allowing rapid reconfiguration of frequency ratios without the settling time issues of analog VCO tuning. Frequency adjustments are made by changing digital control words that directly affect the division ratios, enabling fast frequency switching while maintaining PLL-based frequency stability.
3Device complexity
If single oscillator architecture is used, then hardware cost is reduced, but flexibility in multi-rate clock domain design is limited
Solution Approach 1:
The patent implements a single integer-N PLL architecture that can generate multiple clock frequencies by dynamically reconfiguring the feedback division ratio and output division ratios. This universal frequency synthesizer can serve multiple clock domains with different frequency requirements by programmatically changing the division ratios, eliminating the need for multiple dedicated VCOs while maintaining full multi-rate clock domain flexibility.
Solution Approach 2:
The patent employs dynamic reconfiguration of the PLL parameters, particularly the feedback division ratio and output division ratios, to adapt to different frequency requirements. The system can switch between different frequency outputs by updating the digital control words that define the division ratios, enabling a single oscillator to dynamically serve multiple clock domains with varying frequency needs.
Data Source
AI summary
An all-digital clock generator includes a digitally-controlled clock generator and a processing unit. The digitally-controlled clock generator generates a clock signal in response to an enable signal and a digital signal. The processing unit has a frequency multiplier and a reference signal having a period, digitizes the period to generate a quantized signal, generates the digital signal according to the quantized signal and the frequency multiplier, and generates the enable signal according to the reference signal, the clock signal and the frequency multiplier.