Digital Clock Synchronization Over Asynchronous Packet Networks
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Solution Overview
Problem
Synchronizing clock timing between network elements in Time Division Multiplexed (TDM) networks is challenging due to the non-synchronous nature of packet networks, which can lead to data loss and transmission errors caused by buffer overflow or underflow, especially when packet networks carry TDM traffic.
Innovation Solution
Implementing a method and apparatus using an all-digital phase locked loop with a Digitally Controlled Frequency Selector (DCFS) to synchronize network elements, where a master clock's loop filter output controls the DCFS, and the output is sampled and transmitted to slave clocks to emulate the master clock's state, allowing them to match the frequency without requiring phase-locked loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If packet networks are used to carry TDM traffic, then cost is reduced and deployment is easier, but clock synchronization between network elements deteriorates leading to data loss and transmission errors
Solution Approach 1:
The patent introduces a timing distribution network as an intermediary between the packet network and TDM network elements. This intermediary carries synchronization signals through the packet network to maintain clock synchronization between network elements, thereby enabling cost-effective packet network deployment while preserving reliable TDM traffic transmission.
2Device complexity
If asynchronous packet networks are used, then device complexity is reduced and flexibility increases, but timing precision between network elements deteriorates
Solution Approach 1:
The patent segments the network into different functional domains: asynchronous packet switching domains for flexibility and synchronous timing distribution domains for precision. The timing distribution network operates as a separate segmented system that provides synchronization signals to network elements, allowing each to maintain simple asynchronous operation while achieving precise timing coordination when needed.
3Measurement precision
If TDM networks are synchronized using traditional methods, then timing accuracy is improved, but device complexity increases due to phase-locked loops and elastic buffers
Solution Approach 1:
The patent replaces traditional analog phase-locked loop mechanisms with digital timing synchronization methods. The timing distribution network uses digital signal processing and software-based synchronization algorithms to achieve timing accuracy, eliminating the need for complex analog phase-locked loops and elastic buffers in network elements.
Data Source
AI summary
Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).