Digital Clock Regeneration by Averaged Period Sampling
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Solution Overview
Problem
Existing digital design solutions for stabilizing clock signals, such as phase locked loops (PLLs), require analog components and cannot be integrated into purely digital designs like field-programmable gate arrays (FPGAs), making them costly and inefficient, and there is a lack of all-digital solutions capable of replacing traditional PLL circuits for generating stabilized clock signals.
Innovation Solution
A clock regenerator that includes an averaging unit to calculate an average period length value for the input clock signal over a specified interval, using a sampling clock signal, and an output unit to produce a stabilized clock signal based on this average, which compensates for rounding errors to ensure phase accuracy and responsiveness to frequency fluctuations, allowing for digital integration and cost-efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional phase locked loop (PLL) circuit is used to stabilize clock signals, then frequency and phase stability are improved, but the requirement for analog components increases, making integration into purely digital designs impossible and increasing cost
Solution Approach 1:
The patent replaces the traditional analog PLL circuit with a fully digital clock regenerator implementation. The sampling unit samples the input clock signal at a higher frequency, the averaging unit calculates average period values using digital logic, and the output unit generates the stabilized clock signal digitally. This substitution of analog components with digital logic circuits resolves the contradiction by maintaining clock stability while enabling integration into purely digital designs like FPGAs.
2Measurement precision
If phase picking is used to select the most appropriate phase as the recovered clock, then clock signal quality is improved, but no averaging is performed on the input clock signal, reducing accuracy
Solution Approach 1:
The patent performs preliminary averaging of the input clock signal periods before selecting the final clock phase. The averaging unit calculates the average period value over multiple sampling cycles, and this averaged value is used to determine the output clock phase. This preliminary averaging action improves measurement precision by reducing jitter and noise effects, while the subsequent phase selection maintains clock signal stability.
3Reliability
If oversampling and tracking are used to recover clock signals, then signal quality is improved, but there is no determination of average period time, limiting accuracy for frequency stabilization
Solution Approach 1:
The patent implements a feedback mechanism where the averaging unit continuously calculates the average period of the input clock signal and uses this information to adjust the output clock frequency. The sampling unit samples the input clock, the averaging unit processes these samples to determine average period values, and this feedback information is used by the output unit to generate a stabilized clock signal with accurate frequency control.
4Reliability
If a high-frequency sampling clock is used for oversampling, then clock signal stability is improved, but the complexity of the circuit increases
Solution Approach 1:
The patent segments the clock regeneration function into distinct digital modules: a sampling unit that performs high-frequency sampling, an averaging unit that calculates average period values, and an output unit that generates the stabilized clock. This segmentation allows each module to be optimized independently and facilitates implementation in digital logic circuits, reducing overall circuit complexity while maintaining stability.
Data Source
AI summary
A sampling unit (110) receives an input clock signal (CLKin) having a varying period time, and samples the input clock signal (CLKin) based on a sampling clock signal (CLKsmpl) that has a frequency being substantially higher than an average frequency of the input clock signal (CLKin). The sampling unit (110) produces a respective period length value (PL) for each period of the input clock signal (CLKin). An averaging unit (120) receives a number of period length values (PL) from the sampling unit (110), and based thereon produces an average period length value (PLavg) representing an average period time for the input clock signal (CLKin) over an averaging interval including a number of periods equivalent to said number of period length values (PL). An output unit (151) produces a stabilized output clock signal (CLKout) based on the average period length value (PLavg) and the sampling clock signal (CLKsmpl).