Digital Clock Phase Control for Low-Jitter Frequency Synthesis
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Solution Overview
Problem
Current phase adjustment techniques in phase-locked loops (PLLs) suffer from inaccuracies that lead to excessive jitter and spurious frequencies due to delay mismatches in delay locked loop circuits, affecting the generation of clock signals.
Innovation Solution
A phase control engine incorporating a high-speed multiplexer and phase interpolator minimizes phase errors, using a programmable digital control block with a phase accumulator and stall circuit to generate low jitter synthetic clock signals, which are then interpolated to provide accurate frequency synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay locked loop circuits are used for phase adjustment in PLLs, then frequency synthesis can be achieved, but delay mismatches cause excessive jitter and spurious frequencies
Solution Approach 1:
The phase adjustment function is segmented into multiple independent delay stages, each contributing a small, precise time delay. By dividing the total delay into discrete segments that can be individually controlled and summed, the system achieves fine-grained phase adjustment without the cumulative errors of traditional delay locked loops.
Solution Approach 2:
A digital control mechanism serves as an intermediary between the frequency control input and the oscillator phase adjustment. This digital intermediary precisely calculates and controls the phase shift amount, eliminating the analog delay mismatches that cause jitter and spurious frequencies in conventional PLL circuits.
2Productivity
If traditional phase adjustment techniques are used, then frequency synthesis is possible, but accuracy is insufficient to prevent excess jitter
Solution Approach 1:
The patent replaces traditional analog mechanical delay adjustment mechanisms with a digital control system. The digital phase adjustment circuit calculates and applies precise time delays through digital logic operations, achieving superior phase control accuracy without the physical limitations and tolerances of analog delay lines.
3Reliability
If high precision phase control is implemented, then jitter is reduced, but device complexity increases
Solution Approach 1:
The digital control block performs multiple functions simultaneously: it generates the phase adjustment signal, calculates the required time delay, and controls the delay stages. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby achieving low jitter performance without proportionally increasing overall device complexity.
Data Source
AI summary
Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.