Digital Clock Phase Selection for Low-Power Multi-Phase Output
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Solution Overview
Problem
Conventional phase generators are power-consuming due to their current steering approach, which is inefficient in generating different phases for mixing signals.
Innovation Solution
A digital phase generating apparatus comprising a phase selecting unit and a phase generating unit that selects one of multiple input clocks based on digital signal bits to generate a reference clock, which is then frequency-divided and selectively delayed to produce an output clock with a desired phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a current steering approach is used to generate different phases, then phase generation capability is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the analog current steering mechanism with a digital logic-based phase selection system. The phase generator uses digital control signals to select from pre-generated phase signals through logic circuits (AND gates, multiplexers) instead of using current sources and switches. This substitution of mechanical/analog components with digital logic elements significantly reduces power consumption while maintaining the ability to generate multiple phases.
Solution Approach 2:
The patent pre-generates multiple phase signals (e.g., 0°, 90°, 180°, 270°) in advance using input clocks and stores them in buffer registers. Instead of generating phases dynamically through current steering at the moment of need, the system prepares all possible phase signals beforehand and simply selects the required one through digital logic control. This preliminary generation approach eliminates the need for power-hungry current switching operations during phase transitions.
2Measurement precision
If multiple current sources are used to interpolate phases, then phase resolution is improved, but device complexity increases
Solution Approach 1:
The patent segments the phase generation function into two independent parts: (1) a fixed phase generator that creates a set of discrete phase signals (e.g., 4 phases for QPSK), and (2) a digital phase selector that chooses from these segments based on control bits. This segmentation allows high phase resolution to be achieved simply by increasing the number of discrete phase segments in the lookup table, without requiring complex current interpolation circuits. Each phase segment is generated independently and stored, simplifying the overall device structure.
Data Source
AI summary
A phase generating apparatus generates an output clock having a desired phase according to a digital signal. The apparatus includes a phase selecting unit and a phase generating unit. The phase selecting unit selects one of a plurality of input clocks according to a portion of bits of the digital signal to generate a reference clock. Each of the input clocks respectively has a difference phase. The phase selecting unit divides the frequency of the reference clock, and selectively delays the frequency-divided reference clock according to another portion of bits of the digital signal to generate the output clock.