Digital Clock Recovery in Coherent Receivers
Solution Overview
Problem
Current receiver designs face challenges in achieving acceptable jitter tolerance levels, especially when receiving high data rate signals, due to complex clock recovery processes and limited processing rates, which lead to difficulties in aligning sampling clocks and maintaining signal periodicity.
Innovation Solution
A coherent detection receiver employs digital techniques for clock recovery using a free-running clock for analog-to-digital conversion, followed by digital resampling and phase detection, with a numerically controlled oscillator and digital delay elements to adjust the clock and reduce jitter, allowing for both low and high frequency tolerance through feedback and feed-forward paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a highly parallel receiver implementation is used to handle high data rate signals, then the processing rate is improved, but delays in feedback paths increase and jitter tolerance deteriorates
Solution Approach 1:
The patent replaces the traditional analog phase-locked loop (analog system) with a fully digital clock recovery system. The digital system uses a numerically controlled oscillator (NCO) and digital signal processing to achieve clock recovery, eliminating the mechanical/analog feedback path delays that caused jitter tolerance issues in high-speed parallel implementations.
Solution Approach 2:
The patent introduces a digital delay element as an intermediary component that compensates for feedback path delays in the digital clock recovery system. This digital delay element acts as a mediator to align timing between different processing stages, maintaining jitter tolerance while enabling high-speed parallel processing.
2Use of energy by moving object
If digital techniques are used for clock recovery instead of analog techniques, then power dissipation is reduced and flexibility is improved, but implementation complexity increases
Solution Approach 1:
The patent implements a universal digital clock recovery architecture that can handle multiple baud rates and signal types through software-configurable parameters. The same hardware infrastructure (ADC, NCO, digital delay element) serves multiple functions across different operating conditions, reducing overall system complexity despite the digital implementation.
Solution Approach 2:
The patent achieves flexibility and reduced power consumption by changing operational parameters (sampling rate, delay values, NCO frequency) rather than changing hardware configurations. This allows the system to adapt to different data rates and signal conditions through parameter adjustment, simplifying the overall implementation while maintaining versatility.
3Speed
If the receive data rate is higher than the processing rate of the receiver, then high data rate signal reception is enabled, but clock recovery complexity increases and jitter tolerance deteriorates
Solution Approach 1:
The patent performs preliminary digital resampling of the incoming high-rate signal to a lower processing rate before main signal processing. This preliminary action reduces the data rate early in the processing chain, enabling standard processing rates to handle high-speed inputs while simplifying the clock recovery requirements for subsequent stages.
Solution Approach 2:
The patent segments the clock recovery function into distinct digital components: a digital delay element for coarse timing adjustment and a numerically controlled oscillator for fine frequency and phase control. This segmentation allows each component to operate at optimized rates, reducing overall complexity while supporting high data rate reception.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Digital techniques to recover clock in a coherent receiver using intradyne detection are provided. A free running oscillator clocks an analog to digital converter that is used to convert an input analog signal to digital data. The digital data is resampled using a numerically controlled oscillator clock. Phase detection is performed on the digital data after it is resampled to determine any phase offset. The numerically controlled oscillator clock is adjusted based on the phase offset. In addition, the digital data is delayed after the digital resampling operation using a digital delay element. The phase offset is also fed forward to the digital delay element.