Digital Clock Recovery Circuit for Frequency Offset and Jitter
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Solution Overview
Problem
Conventional clock data recovery (CDR) circuits face challenges in accurately matching transmitter and receiver frequencies due to frequency offsets and jitter issues, leading to phase drifting and increased noise and power consumption.
Innovation Solution
A time-average-frequency based clock data recovery circuit that uses a binary phase detector, digital loop control circuit, and digitally controlled oscillator to generate a recovered clock signal by calculating an average frequency over multiple cycles, eliminating the need for digital-to-analog conversion and reducing the number of generated frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CDR circuits use multiple frequency generation and digital-to-analog conversion, then frequency matching capability is improved, but noise and power consumption increase
Solution Approach 1:
The patent removes the digital-to-analog converter (DAC) from the conventional CDR circuit architecture. By extracting this component, the system eliminates the associated power consumption and noise generation while maintaining frequency matching capability through purely digital frequency generation and comparison mechanisms.
Solution Approach 2:
The patent replaces the analog voltage-controlled oscillator (VCO) and digital-to-analog conversion path with a digitally controlled oscillator (DCO) that operates entirely in the digital domain. This substitution eliminates the need for analog signal generation and conversion, reducing both power consumption and noise while achieving the same frequency synthesis function.
2Measurement precision
If conventional CDR circuits generate multiple frequencies for clock recovery, then frequency tracking accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the complex analog frequency synthesis path including the DAC and analog filtering stages. By taking out these components, the system achieves frequency tracking through a simplified digital control mechanism that uses a single primary frequency generated by the DCO, rather than synthesizing multiple frequencies analogously.
Solution Approach 2:
The patent substitutes the complex analog frequency multiplication and selection circuitry with a digitally controlled frequency synthesis approach. The DCO generates the required clock frequency directly under digital control, eliminating the need for multiple analog oscillators, switches, and filters while maintaining accurate frequency tracking through digital feedback.
3Speed
If conventional CDR circuits use analog voltage control for frequency adjustment, then frequency response speed is improved, but noise increases
Solution Approach 1:
The patent replaces the analog voltage control mechanism with digital frequency control. The DCO adjusts its output frequency in response to digital control signals from the phase detector, eliminating the analog voltage paths that introduce noise. The digital control logic directly modifies the DCO frequency based on phase error detection without requiring analog-to-digital or digital-to-analog conversions.
4Measurement precision
If conventional CDR circuits include digital-to-analog conversion stages, then clock signal quality is improved, but jitter tolerance decreases
Solution Approach 1:
The patent removes the digital-to-analog converter and associated analog signal paths from the CDR circuit. By eliminating these conversion stages, the system avoids introducing additional jitter and noise that typically occur during digital-to-analog transitions. The entire frequency synthesis and control path remains in the digital domain, improving robustness against jitter.
Solution Approach 2:
The patent substitutes the analog clock signal generation path with a fully digital frequency synthesis approach. The DCO generates the recovered clock signal directly in the digital domain, eliminating the need for analog buffering, filtering, and conditioning stages that are susceptible to jitter. This digital-native approach maintains signal integrity and improves jitter tolerance while preserving clock signal quality.
Data Source
AI summary
A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital loop control circuit configured to receive the phase offset signal and output a control signal; and a digital frequency generator configured to receive the control signal and output the recovered clock. A method of clock recovery includes generating a digital phase offset signal from incoming data and feedback clock signals; generating a clock frequency control signal from the phase offset signal; generating a recovered clock in response to the control signal; slowing down the recovered clock when the digital phase offset signal has a first binary state; speeding up the recovered clock when the digital phase offset signal has a second binary state; and holding the recovered clock when the digital phase offset signal has a third binary state.