Digital Clock Recovery Circuit for Low-Power Data Sampling
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Solution Overview
Problem
Existing clock recovery circuits for data transmission without a clock signal require complex mixtures of analog and digital components, leading to high power consumption, which is undesirable for systems with limited power capabilities, such as automated toll payment devices.
Innovation Solution
A fully-digital clock recovery circuit utilizing a delay-locked-loop (DLL) and phase alignment features to generate a clock from incoming data, with power conservation through activation only when valid data is received and no calibration procedure required, employing a simple combinatorial logic circuit to produce a clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If precise local oscillators (PLL arrangements) are used to recover the clock signal from incoming data edges, then the clock recovery accuracy is improved, but the circuit complexity and power consumption increase
Solution Approach 1:
The patent extracts only the essential function of clock recovery from the complex PLL architecture, implementing a simplified digital circuit that detects data edges and generates clock pulses directly without the need for complex phase detection, filtering, and voltage-controlled oscillation components.
Solution Approach 2:
The patent replaces the traditional analog PLL mechanism with a fully digital implementation using logic gates and flip-flops, substituting continuous analog signal processing with discrete digital logic operations to achieve the same clock recovery function with reduced complexity.
2Measurement precision
If precise local oscillators (PLL arrangements) are used to recover the clock signal from incoming data edges, then the clock recovery accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent extracts only the essential function of clock recovery from the complex PLL architecture, implementing a simplified digital circuit that detects data edges and generates clock pulses directly without the need for complex phase detection, filtering, and voltage-controlled oscillation components.
Solution Approach 2:
The patent replaces the traditional analog PLL mechanism with a fully digital implementation using logic gates and flip-flops, substituting continuous analog signal processing with discrete digital logic operations to achieve the same clock recovery function with reduced complexity.
3Use of energy by moving object
If a fully-digital clock recovery circuit is used instead of analog and digital mixture, then the power consumption is reduced, but the measurement precision may be affected
Solution Approach 1:
The patent replaces the traditional analog PLL mechanism with a fully digital implementation using logic gates and flip-flops, substituting continuous analog signal processing with discrete digital logic operations to achieve the same clock recovery function with reduced complexity.
Solution Approach 2:
The patent incorporates feedback mechanisms where the generated clock signal is compared with the incoming data edges, and the phase detector adjusts the clock phase to maintain accurate synchronization, ensuring precision is maintained despite the digital implementation.
4Device complexity
If simple combinatorial logic circuit is used to generate clock signal, then the device complexity is reduced, but the adaptability to different data rates may be limited
Solution Approach 1:
The patent implements dynamic behavior in the digital circuit where the clock generation and phase adjustment adapt automatically to the incoming data rate by detecting edge transitions and adjusting the clock phase accordingly, allowing the simple circuit to handle variable data rates effectively.
Data Source
Figure 1~2
Figure 3
Figure 4~5B
AI summary
A clock recovery circuit (10) comprises an input node (IN) configured to receive a data signal (Data_in) having a data rate and a digital oscillator (22, 24) such as a Delay Lock Loop to produce a local clock signal (CLK) with a frequency higher than the data rate of the data signal (Data_in). A counter (260) clocked by the local clock signal (CLK) is configured to have its count value sampled and then reset at the rising and falling edges of the data signal (Data_in) and a storage block (266) coupled to the counter (260) is configured to store a count value that is is updated (SE) in response to the current sampled count value of the counter (260) lying in an update range between a lower bound (e.g., half the value previously stored minus a count margin) and an upper bound (e.g., the value previously stored plus a count margin). A threshold value set (Edge1, Edge2) is produced as a function of the updated count value stored in the storage block (266). Sampling circuitry (14) configured to receive the data signal (Data_in) at the input node (IN) samples (SI) the data signal (Data_in) at the input node and provide at an output node (OUT) a sampled version (Sampled Data_in) of the data signal (Data_in) at the input node (IN) in response to the count value of the counter (260) reaching any of the threshold values in the threshold value set (Edge1, Edge 2).