Digital Clock Regenerator for Jitter Reduction
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Solution Overview
Problem
Current technologies lack an all-digital solution for stabilizing clock signals, which is essential for digital integration and cost-efficiency, as traditional phase locked loop (PLL) circuits require analog components and are not suitable for purely digital designs.
Innovation Solution
A clock regenerator that includes an averaging unit to calculate an average period length value for the input clock signal, ensuring a stabilized output clock signal by compensating for rounding errors and using a weight function to adjust for frequency fluctuations, allowing for smooth and gradual frequency variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional phase locked loop (PLL) circuit is used to stabilize clock signals, then frequency and phase stability are improved, but the design cannot be integrated into a purely digital system because it requires analog components
Solution Approach 1:
The patent replaces the analog mechanical PLL system with a purely digital clock regenerator that uses digital counters, accumulators, and logic circuits to achieve the same clock signal stabilization function, enabling full digital integration in FPGAs and ASICs
Solution Approach 2:
The invention changes the operating parameters from analog continuous signals to digital discrete values, using digital period length measurements and average calculations to control clock signal stability instead of analog voltage and current adjustments
2Reliability
If analog components are used in PLL circuits, then clock signal stabilization is achieved, but manufacturing cost increases and integration into digital systems becomes difficult
Solution Approach 1:
The patent substitutes analog components with digital logic elements such as counters, accumulators, and digital signal processing units, which can be manufactured using standard digital CMOS processes, reducing manufacturing cost and improving integrability
Solution Approach 2:
The digital clock regenerator uses universal digital building blocks that can be implemented in various digital platforms (FPGAs, ASICs, microcontrollers), making the solution broadly applicable and cost-effective across different manufacturing processes
3Measurement precision
If phase picking is used to select the most appropriate phase as recovered clock, then signal selection is improved, but no averaging is performed on the input clock signal resulting in higher jitter
Solution Approach 1:
The patent performs preliminary averaging of multiple period length measurements before generating the recovered clock signal, preparing a stabilized average value in advance that reduces jitter and improves output clock stability
Solution Approach 2:
The invention implements feedback by continuously measuring input clock period lengths, comparing them to the average, and using the difference to adjust the output clock phase and frequency, creating a self-correcting system that maintains stability
4Adaptability or versatility
If the frequency of the input clock signal varies, then adaptability is improved, but maintaining phase synchronization becomes more difficult
Solution Approach 1:
The patent implements dynamic adaptation by continuously updating the average period length based on current measurements and using this dynamic average to control the output clock frequency, allowing the system to adapt to frequency variations while maintaining phase synchronization through continuous comparison and adjustment
Data Source
Figure 1~3
Figure 4
AI summary
A sampling unit (110) receives an input clock signal (CLKin) having a varying period time, and samples the input clock signal (CLKin) based on a sampling clock signal (CLKsmpl) that has a frequency being substantially higher than an average frequency of the input clock signal (CLKin). The sampling unit (110) produces a respective period length value (PL) for each period of the input clock signal (CLKin). An averaging unit (120) receives a number of period length values (PL) from the sampling unit (110), and based thereon produces an average period length value (PLavg) representing an average period time for the input clock signal (CLKin) over an averaging interval including a number of periods equivalent to said number of period length values (PL). An output unit (151) produces a stabilized output clock signal (CLKout) based on the average period length value (PLavg) and the sampling clock signal (CLKsmpl).