Digital Clock Synchronization Using a Gated Ring Oscillator
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Solution Overview
Problem
Existing synchronization methods in semiconductor devices, such as Delay Locked Loops (DLL) and Phase Locked Loops (PLL), consume excessive power and require many cycles to resynchronize, making them inefficient for power conservation and are often undesirable due to the mixing of analog and digital circuits in manufacturing processes.
Innovation Solution
A digital method using a gated digital ring oscillator that synchronizes data and clock signals without analog circuits, allowing for low power consumption and rapid start/stop functionality, achieving phase alignment through incremental delay adjustments and digital logic implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Delay Locked Loop (DLL) or Phase Locked Loop (PLL) synchronization methods are used, then phase alignment between data output and input clock is achieved, but power consumption increases and resynchronization requires many cycles
Solution Approach 1:
The patent extracts the analog circuitry from the synchronization system and replaces it with digital logic circuits. Specifically, it removes the analog voltage-controlled oscillators and phase detectors from PLL/DLL designs, retaining only the essential phase alignment function through digital delay elements and logic gates that can achieve the same synchronization without continuous power consumption.
Solution Approach 2:
The patent changes the operational parameters of the synchronization system by using digital delay line parameters instead of analog frequency and phase parameters. The digital system adjusts synchronization by selecting from discrete delay values stored in lookup tables, rather than continuously tuning analog parameters, enabling rapid reconfiguration with minimal power consumption.
2Measurement precision
If PLL synchronization method is used, then phase alignment is achieved, but analog and digital circuits are mixed in manufacturing process
Solution Approach 1:
The patent segments the synchronization function into separate digital components: delay elements, lookup tables, and logic control units. This segmentation allows each component to be implemented using standard digital CMOS processes without requiring specialized analog manufacturing steps, simplifying the overall fabrication process while maintaining synchronization precision.
3Loss of energy
If rapid start/stop functionality is required for power conservation, then operation can be stopped, but synchronization is lost and many cycles are required to re-synchronize
Solution Approach 1:
The patent implements preliminary action by pre-calculating and storing optimal delay values in lookup tables before operation begins. When the system needs to restart after being stopped, it can immediately retrieve the pre-computed synchronization parameters from memory rather than performing time-consuming analog tuning, achieving rapid re-synchronization with minimal power consumption during the stop period.
Data Source
AI summary
A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2n where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.