Digital Clock Switching with PLL Phase Compensation
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Solution Overview
Problem
Existing wireless communication systems face inefficiencies in clock switching, leading to resource waste and potential errors due to the use of analog circuits for phase compensation between different clocks, which are difficult to implement and prone to errors.
Innovation Solution
A digital phase locked loop method is employed to determine an average control word based on a preset duration and real frequency tuning word, using it to calculate a compensation phase difference for seamless switching between reference clocks, reducing jitter and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog circuits are used to perform phase compensation between different clocks, then phase compensation can be achieved, but the implementation becomes difficult and errors occur due to phase compensation data errors
Solution Approach 1:
The patent replaces the analog circuit system with a digital processing system. Specifically, it uses a digital phase locked loop to generate phase compensation values and a digital signal processor to apply these compensations, substituting the mechanical/analog phase compensation circuit with a digital computing approach that eliminates implementation difficulties and error-proneness while maintaining compensation accuracy
Solution Approach 2:
The patent introduces an intermediary digital processing layer between the clock sources and the final output. The digital phase locked loop acts as an intermediary that measures phase differences and generates compensation values, which are then applied through another intermediary component (the digital signal processor), creating a buffered, error-resistant path that avoids direct analog circuit errors
2Reliability
If clock switching is performed between different reference clocks, then the operating clock accuracy can be maintained, but chip resources are excessively occupied causing resource waste
Solution Approach 1:
The patent makes the digital phase locked loop and digital signal processor serve multiple functions: they not only perform phase compensation but also manage clock switching, measure phase differences across different clock sources, and generate compensation values dynamically. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall chip resource occupation while maintaining clock switching accuracy
Solution Approach 2:
The patent dynamically changes the phase compensation parameter based on the specific clock switching scenario. Instead of using fixed or excessive resource allocation, the digital phase locked loop adjusts the phase compensation values in real-time according to the actual phase differences measured during clock switching, optimizing resource usage while ensuring accuracy
Data Source
AI summary
The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.